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21-s3- p80c5/c80c5/c80c8 -052002 user's manual s3p80c5/c80c5/c80c8 8-bit cmos microcontrollers revision 1
s3p80c5/c80c5/c80c8 8-bit cmos microcontroller s user's manual revision 1
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3p80c5/c80c5/c80c8 8-bit cmos microcontroller s user's manual, revision 1 publication number: 2 1 - s3 - p80c5/c80c5/c80c8 - 052002 ? 2002 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso- 1400 1 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 440-900 tel: (82)-(31)-209-1934 fax: (82)-(31)-209-1899 home page: http://www.samsungsemi.com printed in the republic of korea
s3p80c5/c80c5/c80c8 microcontroller iii preface the S3C80C5/c80c8 microcontroller user's manual is designed for application designers and progr ammers who are using the S3C80C5/c80c8 microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapter s: chapter 1 product overview chapter 2 address spaces chapter 3 addressing mo des chapter 4 control registers chapter 5 interrupt structure chapter 6 instruction set chapter 1, "product overview," is a high-l evel introduction to S3C80C5/c80c8 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces, the internal register file, and register addressing. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the addressing modes that are supported by the ks88-series cpu . chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt s tructure," describes the S3C80C5/c80c8 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, "instruction set," describes the features and conventions of the instruction set used for all s3c8 -series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3c8-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapter s 1 ? 3 carefully. then, briefly look over the detailed information in chapter s 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the S3C80C5/c80c8 microcontroller. also included in part ii are electrical, mechanical, otp, and development tools data. it has eight chapter s: chapter 7 clock circuit chapter 8 reset and power-down chapter 9 i/o ports chapter 10 ba sic timer and timer 0 chapter 11 timer 1 chapter 1 2 counter a chapter 13 electr ical data chapter 14 mechanical data two order forms are included at the back of this manual to facilitate customer order for S3C80C5/c80c8 microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.

s3p80c5/c80c5/c80c8 microcontroller v table of contents part i ? programming model chapter 1 product overview overview ................................ ................................ ................................ ................................ ................. 1-1 s3p80c5/c80c5/c80c8 microcontroller ................................ ................................ ................................ . 1-1 features ................................ ................................ ................................ ................................ .................. 1-2 cpu ................................ ................................ ................................ ................................ ........................ 1-2 block diagram ................................ ................................ ................................ ................................ ......... 1-3 pin assignments ................................ ................................ ................................ ................................ ...... 1-4 pin descriptions ................................ ................................ ................................ ................................ ....... 1-5 pin circuits ................................ ................................ ................................ ................................ .............. 1-6 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ................. 2-1 program memory (rom) ................................ ................................ ................................ ......................... 2-2 register architecture ................................ ................................ ................................ ............................... 2- 3 register page pointer (pp) ................................ ................................ ................................ ............. 2- 5 register set 1 ................................ ................................ ................................ ................................ . 2- 6 register set 2 ................................ ................................ ................................ ................................ . 2- 6 prime register space ................................ ................................ ................................ ..................... 2 - 7 working registers ................................ ................................ ................................ ........................... 2 - 8 using the register pointers ................................ ................................ ................................ ............ 2 - 9 register addressing ................................ ................................ ................................ ................................ . 2 - 11 common working register area (c0h?cfh) ................................ ................................ .................. 2 - 13 4-bit working register addressing ................................ ................................ ................................ .. 2 - 14 8-bit working register addressing ................................ ................................ ................................ .. 2 - 16 system and user stacks ................................ ................................ ................................ .......................... 2 - 18 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ................. 3-1 register addressing mode (r) ................................ ................................ ................................ ......... 3-2 indirect register addressing mode (ir) ................................ ................................ ........................... 3-3 indexed addressing mode (x) ................................ ................................ ................................ .......... 3-7 direct address mode (da) ................................ ................................ ................................ ............... 3-10 indirect address mode (ia) ................................ ................................ ................................ .............. 3-12 relative address mode (ra) ................................ ................................ ................................ ........... 3-13 immediate mode (im) ................................ ................................ ................................ ...................... 3-14
vi s3p80c5/c80c5/c80c8 microcontroller table of contents (cont inued chapter control registers ................................ ................................ ................. chapter 5 overview ................................ ................................ ................................ 5-1 interrupt types ................................ ................................ 5-2 interrupt structure ................................ ................................ 5-3 interrupt vector addresses ................................ ................................ 5-5 enable/disable interrupt instructions (ei, di) ................................ ................... system-level interrupt control registers ................................ ........................ 5-7 ................................ ................................ .. 5-8 ................................ ................................ 5-9 system mode register (sym) ................................ ................................ 5-10 interrupt mask register (imr) ................................ ................................ 5-11 interrupt priority register (ipr) ................................ ................................ 5-12 interrupt request register (irq) ................................ ................................ 5-14 interrupt pending function types ................................ ................................ 5-15 interrupt source polling sequence ................................ ................................ 5-16 interrupt service routines ................................ ................................ 5-16 generating interrupt vector addresses ................................ ............................ nesting of vectored interrupts ................................ ................................ ......... instruction pointer (ip) ................................ ................................ ..................... 7 fast interrupt processing ................................ ................................ 5-17 chapter instruction set overview ................................ ................................ ................. 6-1 ................................ ................................ ................................ ...... register addressing ................................ ................................ ........................ addressing modes ................................ ................................ ........................... flags register (flags) ................................ ................................ .................. flag descriptions ................................ ................................ ............................. instruction set notation ................................ ................................ ................... condition codes ................................ ................................ .............................. instruction descriptions ................................ ................................ ...................
s3p80c5/c80c5/c80c8 microcontroller vii table of contents (continued) part ii hardware descriptions chapter 7 clock circuit overview ................................ ................................ ................................ ................................ ................. 7-1 system clock circuit ................................ ................................ ................................ ....................... 7-1 clock status during power-down modes ................................ ................................ ......................... 7-2 system clock control register (clkcon) ................................ ................................ ...................... 7-3 chapter 8 reset reset and power-down system reset ................................ ................................ ................................ ................................ .......... 8-1 lvd reset ................................ ................................ ................................ ................................ ....... 8-1 interrupt with reset (intr) ................................ ................................ ................................ .............. 8-2 watch-dog timer reset ................................ ................................ ................................ .................. 8-2 power-on reset (por) ................................ ................................ ................................ .................... 8-2 system reset operation ................................ ................................ ................................ ................. 8-3 hardware reset values ................................ ................................ ................................ ................... 8-4 power-down modes ................................ ................................ ................................ ................................ . 8-6 stop mode ................................ ................................ ................................ ................................ ....... 8-6 using por to release stop mode ................................ ................................ ................................ ... 8-6 using an intr to release stop mode ................................ ................................ ............................. 8-6 idle mode ................................ ................................ ................................ ................................ ........ 8-9 summary table of stop mode, and idle mode ................................ ................................ ................. 8-10 chapter 9 i/o ports overview ................................ ................................ ................................ ................................ ................. 9-1 port data registers ................................ ................................ ................................ ......................... 9-2 pull-up resistor enable registers ................................ ................................ ................................ ... 9-2 port 0 ................................ ................................ ................................ ................................ .............. 9-4 port 0 interrupt enable register (p0int) ................................ ................................ ......................... 9-5 port 0 interrupt pending register (p0pnd) ................................ ................................ ...................... 9-5 port 1 ................................ ................................ ................................ ................................ .............. 9-7 port 2 ................................ ................................ ................................ ................................ .............. 9-9 chapter 10 basic timer and timer 0 module overview ................................ ................................ ................................ ................................ ..... 10-1 basic timer control register (btcon) ................................ ................................ ............................... 10-1 basic timer function description ................................ ................................ ................................ ........ 10-3 timer 0 control register (t0con) ................................ ................................ ................................ ...... 10-3 timer 0 function description ................................ ................................ ................................ ............... 10-5
viii s3p80c5/c80c5/c80c8 microcontroller table of contents (concluded) chapter 11 timer 1 overview ................................ ................................ ................................ ................................ ................. 11-1 timer 1 overflow interrupt ................................ ................................ ................................ ............... 11-2 timer 1 match interrupt ................................ ................................ ................................ ................... 11-2 timer 1 control register (t1con) ................................ ................................ ................................ .. 11-4 chapter 12 counter a overview ................................ ................................ ................................ ................................ ................. 12-1 counter a control register (cacon) ................................ ................................ .............................. 12-3 counter a pulse width calculations ................................ ................................ ................................ 12-4 chapter 1 3 electrical data overview ................................ ................................ ................................ ................................ ................. 13-1 chapter 14 mechanical data overview ................................ ................................ ................................ ................................ ................. 14-1
s3p80c5/c80c5/c80c8 microcontroller ix list of figures figure title page number number 1-1 block diagram ................................ ................................ ................................ ........ 1-3 1-2 pin assignment diagram (24-pin sop/sdip package) ................................ .......... 1-4 1-3 pin circuit type 1 (port 0) ................................ ................................ ...................... 1-6 1-4 pin circuit type 2 (port 1) ................................ ................................ ...................... 1-7 1-5 pin circuit type 3 (p2.0) ................................ ................................ ........................ 1-8 1-6 pin circuit type 4 (p2.1) ................................ ................................ ........................ 1-9 1-7 pin circuit type 5 (p2.2) ................................ ................................ ........................ 1-10 2-1 program memory address space ................................ ................................ ........... 2-2 2-2 internal register file organization ................................ ................................ ......... 2-4 2-3 regis ter page pointer (pp) ................................ ................................ .................... 2-5 2-4 set 1, set 2, and prime area register map ................................ ............................ 2-7 2-5 8-byte working register areas (slices) ................................ ................................ .. 2-8 2-6 contiguous 16-byte working register block ................................ .......................... 2-9 2-7 non-contiguous 16-byte working register block ................................ ................... 2-10 2-8 16-bit register pair ................................ ................................ ................................ 2-11 2-9 register file addressing ................................ ................................ ......................... 2-12 2-10 common working register area ................................ ................................ ............ 2-13 2-11 4-bit working register addressing ................................ ................................ ......... 2-15 2-12 4-bit working register addressing example ................................ .......................... 2-15 2-13 8-bit working register addressing ................................ ................................ ......... 2-16 2-14 8-bit working register addressing ex ample ................................ .......................... 2-17 2-15 stack operations ................................ ................................ ................................ .... 2-18 3-1 register addressing ................................ ................................ ............................... 3-2 3-2 working register addressing ................................ ................................ ................. 3-2 3-3 indirect register addressing to register file ................................ .......................... 3-3 3-4 indirect register addressing to program memory ................................ ................... 3-4 3-5 indirect working register addressing to register file ................................ ............ 3-5 3-6 indirect working register addressing to program or data memory ........................ 3-6 3-7 indexed addressing to register file ................................ ................................ ....... 3-7 3-8 indexed addressing to program or data memory with short offset ........................ 3-8 3-9 indexed addressing to program or data memory ................................ ................... 3-9 3-10 direct addressing for load instructions ................................ ................................ .. 3-10 3-11 direct addressing for call and jump instructions ................................ .................... 3-11 3-12 indirect addressing ................................ ................................ ................................ . 3-12 3-13 relative addressing ................................ ................................ ............................... 3-13 3-14 immediate addressing ................................ ................................ ............................ 3-14 4-1 register description format ................................ ................................ ................... 4-4
x s3p80c5/c80c5/c80c8 microcontroller list of figures (continued) figure title page number number 5-1 ks88-series interrupt types ................................ ................................ ................... 5-2 5-3 rom vector address area ................................ ................................ ..................... 5-5 5-2 interrupt structure ................................ ................................ ................................ .. 5-4 5-4 interrupt function diagram ................................ ................................ ..................... 5-8 5-5 system mode register (sym) ................................ ................................ ................ 5-10 5-6 interrupt mask register (i mr) ................................ ................................ ................. 5-11 5-7 interrupt request priority groups ................................ ................................ ........... 5-12 5-8 interrupt priority register (ipr) ................................ ................................ ............... 5-13 5-9 interrupt request register (irq) ................................ ................................ ............ 5-14 6-1 system flags register (flags) ................................ ................................ ............. 6-6 7-1 main oscillator circuit (external crystal or ceramic resonator) ............................. 7-1 7-2 external clock circuit ................................ ................................ ............................. 7-1 7-3 system clock circuit diagram ................................ ................................ ................ 7-2 7-4 system clock control register (clkcon) ................................ ............................. 7-3 8-1 reset block diagram ................................ ................................ .............................. 8-1 8-2 power-on reset circuit ................................ ................................ ........................... 8-2 8-3 timing diagram for power-on reset circuit ................................ ............................ 8-3 9-1 s3p80c5/c80c5/c80c8 i/o port 0 data register format ................................ ...... 9- 2 9-2 s3p80c5/c80c5/c80c8 i/o port 1 data register format ................................ ...... 9-3 9-3 port 0 high-by te control register (p0conh) ................................ ......................... 9-4 9-4 port 0 low-by te control register (p0conl) ................................ .......................... 9-5 9-5 port 0 external interr upt control register (p0int) ................................ .................. 9-6 9-6 port 0 external interr upt pending register (p0pnd) ................................ ............... 9-7 9-7 port 1 high-by te control register (p1conh) ................................ ......................... 9-7 9-8 port 1 low-by te control register (p1conl) ................................ .......................... 9-8 9-9 por t 2 control register (p2con) ................................ ................................ ............ 9-9 9-10 port 2 data register (p2) ................................ ................................ ....................... 9-10
s3p80c5/c80c5/c80c8 microcontroller xi list of figures (concluded) figure title page number number 10-1 basic timer control register (bt con) ................................ ................................ .. 10-2 10-2 timer 0 control register (t0con) ................................ ................................ ......... 10-4 10-3 simplified timer 0 function diagram: interval timer mode ................................ .... 10-5 10-4 simplified timer 0 function diagram: pwm mode ................................ ................. 10-6 11-1 simplified timer 1 function diagram: interval timer mode ................................ .... 11-2 11-2 timer 1 block diagram ................................ ................................ ........................... 11-3 11-3 timer 1 control register (t1con) ................................ ................................ ......... 11-4 11-4 timer 1 registers ................................ ................................ ................................ ... 11-5 12-1 counter a block diagram ................................ ................................ ....................... 12-2 12-2 counter a control register (cacon) ................................ ................................ ..... 12-3 12-3 counter a registers ................................ ................................ ............................... 12-4 12-4 counter a output flip-flop waveforms in repeat mod e ................................ ........ 12-5 13-1 input timing for external interrupts (port 0) ................................ ............................ 13-5 13-2 operating voltage range ................................ ................................ ...................... 13-6 14-1 24-pin sop package mechanical data ................................ ................................ .. 14-1 14-2 24-pin sdip package mechanical data ................................ ................................ .. 14-2

s3p80c5/c80c5/c80c8 microcontroller xiii list of tables table title page number number 1-1 pin descriptions ................................ ................................ ................................ ..... 1-5 2-1 register type summary ................................ ................................ ......................... 2-3 4-1 mapped registers (set1) ................................ ................................ ........................ 4-2 5-1 interrupt vectors ................................ ................................ ................................ ..... 5-6 5-2 interrupt control register overview ................................ ................................ ....... 5-7 5-3 interrupt source control and data registers ................................ ........................... 5-9 6-1 instruction group summary ................................ ................................ .................... 6-2 6-2 flag notation conventi ons ................................ ................................ ..................... 6-8 6-3 instruction set symbols ................................ ................................ .......................... 6-8 6-4 instruction notation conventions ................................ ................................ ............ 6-9 6-5 opcode quick reference ................................ ................................ ....................... 6-10 6-6 condition codes ................................ ................................ ................................ ..... 6-12 8-1 set 1 register values after reset ................................ ................................ .......... 8-4 8-2 summary of each mode ................................ ................................ ......................... 8-10 9-1 s3p80c5/c80c5/c80c8 port configuration overview ................................ ........... 9-1 9-2 port data register summary ................................ ................................ .................. 9-2 13-1 absolute maximum ratings ................................ ................................ .................... 13-2 13-2 d.c. electrical characteristics ................................ ................................ ................ 13-2 13-3 characteristics of low voltage detect circuit ................................ .......................... 13-4 13-4 data retention supply voltage in stop mode ................................ ......................... 13-4 13-5 input/output capacitance ................................ ................................ ....................... 13-4 13-6 a.c. electrical characteristics ................................ ................................ ................ 13-4 13-7 oscillation characteristics ................................ ................................ ...................... 13-5 13-8 oscillation stabilization time ................................ ................................ ................. 13-6

s3p80c5/c80c5/c80c8 microcontroller xv list of programming tips description page number chapter 2: address spaces setting the register pointers ................................ ................................ ................................ ............... 2-9 using the rps to calculate the sum of a series of registers ................................ ............................... 2-10 addressing the common working register area ................................ ................................ ................. 2-14 standard stack operations using push and pop ................................ ................................ .............. 2-19 chapter 8: reset reset and power-down to divide stop mode releasing and por ................................ ................................ ......................... 8-8 chapter 10: basic timer and timer 0 configuring the basic timer ................................ ................................ ................................ ................ 10-8 programming timer 0 ................................ ................................ ................................ .......................... 10-9 chapter 12: counter a to generate 38 khz, 1/3duty signal through p2.1 ................................ ................................ .............. 12-6 to generate a one pulse signal through p2.1 ................................ ................................ ................... 12-7

s3p80c5/c80c5/c80c8 microcontroller xvii list of register descriptions register full register name page identifier number btcon basic timer control register ................................ ................................ .................. 4-5 cacon counter a control register ................................ ................................ ..................... 4-6 clkcon system clock control register ................................ ................................ ............... 4-7 emt external memory timing register ................................ ................................ .......... 4-8 flags system flags register ................................ ................................ ........................... 4-9 imr interrupt mask register ................................ ................................ .......................... 4-10 iph instruction pointer (high byte ) ................................ ................................ ............... 4-11 ipl instruction pointer (low byte ) ................................ ................................ ................ 4-11 ipr interrupt priority register ................................ ................................ ........................ 4-12 irq interrupt request register ................................ ................................ ...................... 4-13 p0con h port 0 control register (high byte ) ................................ ................................ ........ 4-14 p0 conl port 0 control register (low byte ) ................................ ................................ ......... 4-15 p0int port 0 interrupt control register ................................ ................................ ............. 4-16 p0pnd port 0 interrupt pending register ................................ ................................ ........... 4-17 p0pur port 0 pull-up resistor enable register ................................ ................................ .. 4-18 p1con h port 1 control register (high byte ) ................................ ................................ ........ 4-19 p1 con l port 1 control register (low byte ) ................................ ................................ ......... 4-20 p1pur port 1 pull-up resistor enable regi ster ................................ ................................ . 4-21 p2con port 2 control register ................................ ................................ ........................... 4-22 pp register page pointer ................................ ................................ ............................ 4-23 rp0 register pointer 0 ................................ ................................ ................................ ... 4-24 rp1 register pointer 1 ................................ ................................ ................................ ... 4-24 spl stack pointer (low byte) ................................ ................................ ........................ 4-25 stopcon stop control register ................................ ................................ ............................. 4-25 sym system mode register ................................ ................................ ........................... 4-26 t0con timer 0 control register ................................ ................................ ........................ 4-27 t1con timer 1 control register ................................ ................................ ........................ 4-28

s3p80c5/c80c5/c80c8 microcontroller xix list of instruction descriptions instruction full register name page mnemonic number adc add with carry ................................ ................................ ................................ ........ 6-14 add add ................................ ................................ ................................ ........................ 6-15 and logical and ................................ ................................ ................................ ........... 6-16 band bit and ................................ ................................ ................................ .................. 6-17 bcp bit compare ................................ ................................ ................................ ........... 6-18 bitc bit complement ................................ ................................ ................................ ..... 6-19 bitr bit reset ................................ ................................ ................................ ................ 6-20 bits bit set ................................ ................................ ................................ .................... 6-21 bor bit or ................................ ................................ ................................ .................... 6-22 btjrf bit test, jump relative on false ................................ ................................ ............ 6-23 btjrt bit test, jump relative on true ................................ ................................ ............. 6-24 bxor bit xor ................................ ................................ ................................ .................. 6-25 call call procedure ................................ ................................ ................................ ....... 6-26 ccf complement carry flag ................................ ................................ ......................... 6-27 clr clear ................................ ................................ ................................ ...................... 6-28 com complement ................................ ................................ ................................ ........... 6-29 cp compare ................................ ................................ ................................ ................ 6-30 cpije compare, increment, and jump on equal ................................ .............................. 6-31 cpijne compare, increment, and jump on non-equal ................................ ....................... 6-32 da decimal adjust ................................ ................................ ................................ ....... 6-33 dec decrement ................................ ................................ ................................ ............. 6-35 decw decrement word ................................ ................................ ................................ .... 6-36 di disable interrupts ................................ ................................ ................................ ... 6-37 div divide (unsigned) ................................ ................................ ................................ ... 6-38 djnz decrement and jump if non-zero ................................ ................................ .......... 6-39 ei enable interrupts ................................ ................................ ................................ .... 6-40 enter enter ................................ ................................ ................................ ...................... 6-41 exit exit ................................ ................................ ................................ ........................ 6-42 idle idle operation ................................ ................................ ................................ ........ 6-43 inc increment ................................ ................................ ................................ ............... 6-44 incw increment word ................................ ................................ ................................ ..... 6-45 iret interrupt return ................................ ................................ ................................ ...... 6-46 jp jump ................................ ................................ ................................ ...................... 6-47 jr jump relative ................................ ................................ ................................ ........ 6-48 ld load ................................ ................................ ................................ ....................... 6-49 ldb load bit ................................ ................................ ................................ .................. 6-51
xx s3p80c5/c80c5/c80c8 microcontroller list of instruction descriptions (continued) instruction full register name page mnemonic number ldc/lde load memory ................................ ................................ ................................ ......... 6-52 ldcd/lded load memory and decrement ................................ ................................ ................ 6-54 ldci/ldei load memory and increment ................................ ................................ .................. 6-55 ldcpd/ldepd load memory with pre- decrement ................................ ................................ ......... 6-56 ldcpi/ldepi load memory with pre-increment ................................ ................................ ........... 6-57 ldw load word ................................ ................................ ................................ ............. 6-58 mult multiply (unsigned) ................................ ................................ ................................ . 6-59 next next ................................ ................................ ................................ ....................... 6-60 nop no operation ................................ ................................ ................................ .......... 6-61 or logical or ................................ ................................ ................................ ............. 6-62 pop pop from stack ................................ ................................ ................................ ....... 6-63 popud pop user stack (decrementing) ................................ ................................ ............. 6-64 popui pop user stack (incrementing) ................................ ................................ ............... 6-65 push push to stack ................................ ................................ ................................ ......... 6-66 pushud push user stack (decrementing) ................................ ................................ ............ 6-67 pushui push user stack (incrementing) ................................ ................................ ............. 6-68 rcf reset carry flag ................................ ................................ ................................ .... 6-69 ret return ................................ ................................ ................................ .................... 6-70 rl rotate left ................................ ................................ ................................ ............. 6-71 rlc rotate left through carry ................................ ................................ ....................... 6-72 rr rotate right ................................ ................................ ................................ ........... 6-73 rrc rotate right through carry ................................ ................................ ..................... 6-74 sb0 select bank 0 ................................ ................................ ................................ ......... 6-75 sb1 select bank 1 ................................ ................................ ................................ ......... 6-76 sbc subtract with carry ................................ ................................ ................................ . 6-77 scf set carry flag ................................ ................................ ................................ ........ 6-78 sra shift right arithmetic ................................ ................................ .............................. 6-79 srp/srp0/srp1 set register pointer ................................ ................................ ............................... 6-80 stop stop operation ................................ ................................ ................................ ....... 6-81 sub subtract ................................ ................................ ................................ .................. 6-82 swap swap nibbles ................................ ................................ ................................ ......... 6-83 tcm test complement under mask ................................ ................................ ................ 6-84 tm test under mask ................................ ................................ ................................ ..... 6-85 wfi wait for interrupt ................................ ................................ ................................ .... 6-86 xor logical exclusive or ................................ ................................ ............................. 6-87
s3p80c5/c80c5/c80c8 product overview 1- 1 1 product overview overview samsung's s3c8-series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. important cpu features include: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. s3p80c5/c80c5/c80c8 microcontroller the s3p80c5/c80c5/c80c8 single-chip cmos microcontroller is fabricated using a highly advanced cmos process and is based on samsung's newest cpu architecture. the S3C80C5/c80c8 is the microcontroller which has mask-programmable rom. the s3p80c5 is the microcontroller which has one-time-programmable eprom. using a proven modular design approach, samsung engineers developed the s3p80c5/c80c5/c80c8 by integrating the following peripheral modules with the powerful sam87 rc core: ? three programmable i/o ports, including two 8 -bit ports and one 3-bit port, for a total of 19 pins. ? internal lvd circuit and eight bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). ? one 8-bit timer/counter and one 16-bit timer/counter w ith selectable operating modes. ? one 8-bit counter with auto-reload function and one-shot or repeat control. the s3p80c5/c80c5/c80c8 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. it is currently available in a 24-pin sop and sdip package.
product overview s3 p80c5/c80c5/c80c8 1- 2 features cpu sam87rc cpu core memory program memory (rom) ? s3c80c8: 8-kbyte (0000h?1fffh) ? S3C80C5: 15,872 byte (0000h?3e00h) data memory: 256-byte ram instruction set 78 instructions idle and stop instructions added for power- down modes instruction execution time 1000 ns at 4-mhz f osc (minimum) interrupts 13 interrupt sources with 10 vector. 5 level, 10 vector interrupt structure i/o ports two 8-bit i/o ports (p0-p1) and one 3-bit port (p2) for a total of 19 bit-programmable pins eight input pins for external interrupts carrier frequency generator one 8-bit counter with auto-reload function and one-shot or repeat control (counter a) back-up mode when v dd is lower than v lvd , the chip enters back-up mode to block oscillation and reduce the current consumption. timers and timer/counters one programmable 8-bit basic timer (bt) for oscillation stabilization control or watchdog timer function one 8-bit timer/counter (timer 0) with two operating modes; interval mode and pwm mode. one 16-bit timer/counter with one operating modes; interval mode low voltage detect circuit low voltage detect for reset or back-up mode. low level detect voltage ? S3C80C5/c80c8: 1.90 v ( typ) 200 mv auto reset function reset occurs when stop mode is released by p0. when a falling edge is detected at port 0 during stop mode, system reset occurs. operating temperature range ? ?40 c to + 85 c operating voltage range 1.7 v to 3.6 v at 4 mhz f osc package type 24-pin sop/sdip
s3p80c5/c80c5/c80c8 product overview 1- 3 block diagram 8-bit basic timer p0.0-p0.7/int0-int4 p1.0-p1.7 port i/o and interrupt control sam87ri cpu internal bus x in x out port 0(intr) port 1 main osc p2.0/t0pwm 15-kbyte rom 256-byte register file 8-bit timer/ counter 16-bit timer/ counter port 2 carrier generator (counter a) p2.1/rem p2.2 lvd test figure 1-1. block diagram
product overview s3 p80c5/c80c5/c80c8 1- 4 pin assignments v ss x in x out test p0.0/int0/intr p0.1/int1/intr reset reset /p0.2/int2/intr p0.3/int3/intr p0.4/int4/intr p0.5/int4/intr p0.6/int4/intr p0.7/int4/intr S3C80C5/c80c8 24-s op/sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 v dd p2.2 p2.1/rem/ sclk p2.0/t0pwn/t0ck/ sdat p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 24 23 22 21 20 19 18 17 16 15 14 13 figure 1-2. pin assignment diagram (24-pin sop/sdip package)
s3p80c5/c80c5/c80c8 product overview 1- 5 pin descriptions table 1-1. pin descriptions pin names pin type pin description circuit type 24-pin number shared functions p0.0?p0.7 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors are assignable by software. pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. interrupt with reset(intr) is assigned to port 0. 1 5?12 int0 ? int4/intr p1.0?p1.7 i/o i/o port with bit-programmable pins. configurable to input mode or output mode. pin circuits are either push-pull or n- channel open-drain type. pull-up resistors are assignable by software. 2 13?20 p2.0 p2.1 p2.2 i/o 3-bit i/o port with bit-programmable pins. configurable to input mode, push-pull output mode, or n-channel open-drain output mode. input mode with pull-up resistors are assignable by software. the two pins of port 2 have high current drive capability. 3 4 5 21?23 rem/t0ck x in , x out ? system clock input and output pins ? 2, 3 ? test i test signal input pin (for factory use only; must be connected to v ss ). ? 4 ? v dd ? power supply input pin ? 24 ? v ss ? ground pin ? 1 ?
product overview s3 p80c5/c80c5/c80c8 1- 6 pin circuits v dd pull-up enable v dd input/output pull-up resistor output disable data v ss noise filter external interrupt stop intr (interrupt with reset) figure 1-3. pin circuit type 1 (port 0) note interrupt with reset (intr) is assigned to port 0 of s3p80c5/c80c5/c80c8. it is designed to release stop status with reset. when the falling/rising edge is detected at any pin of port 0 during stop status, non vectored interrupt intr signal occurs, after then system reset occurs automatically. it is designed for a application which are using ?stop mode? like remote controller. if stop mode is not used, intr do not operates and it can be discarded.
s3p80c5/c80c5/c80c8 product overview 1- 7 v dd pull-up enable v dd input/output pull-up resistor output disable data v ss noise filter normal input open-drain figure 1-4. pin circuit type 2 (port 1) v dd pull-up enable v dd p2.0/t0pwn pull-up resistor (typical 21k w ) open-drain port 2.0 data v ss m u x p2.0 input output disable data t0_pwn p2con.0 figure 1-5. pin circuit type 3 (p2.0)
product overview s3 p80c5/c80c5/c80c8 1- 8 v dd pull-up enable v dd p2.1/rem/t0ck pull-up resistor (typical 21k w ) open-drain port 2.1 data v ss p2.1 input m u x p2con.1 data output disable noise filter t0ck caof(cacon.0) carrier on/off (p2.5) figure 1-6. pin circuit type 4 (p2.1) v dd pull-up enable v dd in/out pull-up resistor (typical 21k w ) open-drain v ss normal input output disable data figure 1-7. pin circuit type 5 (p2.2)
s3p80c5/c80c5/c80c8 address spaces 2- 1 2 address spaces overview the s3p80c5/c80c5/c80c8 microcontroller has two types of address space: ? internal program memory (rom) ? internal register file a 16-bit address bus supports program memory operations. a separate 8-bit register bus carries addresses and data between the cpu and the register file. the S3C80C5 has an internal 15,872 byte programmable rom, the s3c80c8 has an internal 8-kbyte programmable rom. an external memory interface is not implemented. the 256-byte physical ram space is expanded into an addressable area of 320 bytes by the use of addressing modes. there are 312 mapped registers in the internal register file. of these, 272 are for general-purpose use. (this number includes a 16-byte working register common area that is used as a " scratch area" for data operations, a 256 prime register area that is used for general purpose and stack operation). eighteen 8-bit registers are used for cpu and system control and 22 registers are mapped peripheral control and data registers.
address spaces s3p 80c5/c80c5/c80c8 2- 2 program memory (rom) program memory stores program code or table data. the S3C80C5 has 15, 872 bytes of internal programmable program memory, and the program memory address range is therefore 0000h-3e00h of rom. the s3c80c8 has 8-kbyte (0000h-1fffh) of internal programmable program memory (see figure 2-1). the first 256 bytes of the rom (0h?0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if you do use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations. the rom address at which program execution starts after a reset is 0100h. 15,872 15-kbyte rom 8-kbyte rom interrupt vector area 8,191 255 0 3e00h 1fffh 0ffh 0h (decimal) (hex) s3c80c8 S3C80C5 figure 2-1. program memory address space
s3p80c5/c80c5/c80c8 address spaces 2- 3 register architecture the s3p80c5/c80c5/c80c8 register file has 312 registers. the upper 64 bytes register files are addressed as system control register and working register. the lower 192-byte area of the physical register file(00h?bfh) contains freely-addressable, general-purpose registers called prime registers . it can be also used for stack operation. the extension of register space into separately addressable sets is supported internally by addressing mode restrictions. specific register types and the area (in bytes) they occupy in the s3p80c5/c80c5/c80c8 internal register space are summarized in table 2-1. table 2-1. s3p80c5/c80c5/c80c8 register type summary register type number of bytes general-purpose registers (including the 16-byte common working register area, the 256-byte prime register area.) 272 cpu and system control registers 18 mapped clock, peripheral, and i/o control and data registers 22 total addressable bytes 312
address spaces s3p 80c5/c80c5/c80c8 2- 4 set 2 set 1 ~ bfh 00h prime data registers (all addressing modes) general-purpose data register (indirect register or indexed addressing modes or stack operations) ffh c0h 192-bytes ffh c0h system and peripheral control registers (register addressing mode) system registers (register addressing mode) 64-bytes 256-bytes ~ ~ working registers (working register addressing mode) cfh d0h dfh e0h figure 2-2. internal register file organization
s3p80c5/c80c5/c80c8 address spaces 2- 5 register page pointer (pp) the s3c8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 15 separately addressable register pages. page addressing is controlled by the register page pointer (pp, dfh). in the s3p80c5/c80c5/c80c8 microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to "page 0." following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always '0000', automatically selecting page 0 as the source and destination page for register addressing. these page pointer (pp) register settings, as shown in figure 2-3, should not be modified during normal operation. register page pointer (pp) dfh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb dectination register page selection bits: 0 0 0 0 destination: page 0 source register page selection bits: 0 0 0 0 source: page 0 note : in the S3C80C5/c80c8 microcontroller, only pate 0 is implemented. a hardware reset operation writes the 4-bit destination and source values shown above to the register pate pointer. these values should not be modified. figure 2-3. register page pointer (pp)
address spaces s3p 80c5/c80c5/c80c8 2- 6 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. in some s3c8-series microcontrollers, the upper 32-byte area of this 64-byte space (e0h?ffh) is divided into two 32-byte register banks, bank 0 and bank 1 . the set register bank instructions sb0 or sb1 are used to address one bank or the other. in the s3p80c5/c80c5/c80c8 microcontroller, bank 1 is not implemented. a hardware reset operation therefore always selects bank 0 addressing, and the sb0 and sb1 instructions are not necessary. the upper 32-byte area of set 1 (ffh?e0h) contains 26 mapped system and peripheral control registers. the lower 32-byte area contains 16 system registers (dfh?d0h) and a 16-byte common working register area (cfh? c0h). you can use the common working register area as a "scratch" area for data operations being performed in other areas of the register file. registers in set 1 locations are directly accessible at all times using the register addressing mode. the 16-byte working register area can only be accessed using working register addressing. (for more information about working register addressing, please refer to section 3, "addressing modes," .) register set 2 the same 64-byte physical space that is used for set 1 locations c0h?ffh is logically duplicated to add another 64 bytes of register space. this expanded area of the register file is called set 2 . all set 2 locations (c0h?ffh) are addressed as part of page 0 in the s3p80c5/c80c5/c80c8 register space. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: you can use only register addressing mode to access set 1 locations; to access registers in set 2, you must use register indirect addressing mode or indexed addressing mode. the set 2 register area is commonly used for stack operations.
s3p80c5/c80c5/c80c8 address spaces 2- 7 prime register space the lower 192 bytes of the 256-byte physical internal register file (00h?bfh) is called the prime register space or, more simply, the prime area . you can access registers in this address using any addressing mode. (in other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) all registers in prime area locations are addressable immediately following a reset. ffh c0h 00h set 2 prime register space ffh d0h c0h set 1 fch e0h general-purpose registers cpu and system registers peripheral control registers figure 2-4. set 1, set 2 and prime area register map
address spaces s3p 80c5/c80c5/c80c8 2- 8 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." each slice consists of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slices can be selected at any one time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers; r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers; r0?r15) all of the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file. the base addresses for the two selected 8-byte register slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block . 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 slice 31 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 2 slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2-5. 8-byte working register areas (slices)
s3p80c5/c80c5/c80c8 address spaces 2- 9 using the register pointers register pointers rp0 and rp1, mapped to addresses d6h and d7h in set 1, are used to select two movable 8 -byte working register slices in the register file. after a reset, they point to the working register common area: rp0 points to addresses c0h?c7h, and rp1 points to addresses c8h?cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction (see figures 2-6 and 2-7). with working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by rp0 and rp1. you cannot, however, use the register pointers to select a working register space in set 2, c0h?ffh, because these locations can be accessed only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, we recommend that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). in some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to the either of the two 8-byte slices in the working register block, you can define the working register area very flexibly to support program requirements. f f programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h, srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? 0f8h fh (r15) 0h (r0) 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice 8-byte slice figure 2-6. contiguous 16-byte working register block
address spaces s3p 80c5/c80c5/c80c8 2- 10 16-byte contiguous working register block register file contains 32 8-byte slices 0 0 0 0 0 x x x rp1 1 1 1 1 0 x x x rp0 0h (r0) 7h (r15) f0h (r0) f7h (r7) 8-byte slice 8-byte slice figure 2-7. non-contiguous 16-byte working register block f f programming tip ? using the rps to calculate the sum of a series of registers calculate the sum of registers 80h?85h using the register pointer. the register addresses 80h through 85h contains the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? (80h) + (82h) + c adc 80h,83h ; 80h ? (80h) + (83h) + c adc 80h,84h ; 80h ? (80h) + (84h) + c adc 80h,85h ; 80h ? (80h) + (85h) + c now, the sum of the six registers is also located in register 80h. however, this instruction string takes 15 bytes of instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.
s3p80c5/c80c5/c80c8 address spaces 2- 11 register addressing the s3c8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. working register addressing differs from register addressing because it uses a register pointer to identify a specific 8 -byte working register space in the internal register file and a specific 8-bit register within that space. msb rn lsb rn+1 n = even address figure 2-8. 16-bit register pair
address spaces s3p 80c5/c80c5/c80c8 2- 12 rp1 rp0 00h c0h bfh each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (that is, to the common working register area). ffh c0h set 2 cfh d7h d6h set 1 ffh d0h special-purpose registers general-purpose register register pointers control registers all addressing modes page 0 indirect register, indexed addressing modes page 0 register addressing only can be pointed by register pointer prime registers system registers note: only page 0 is implemented. page 0 contains all of the addressable registers in the internal register file. figure 2-9. register file addressing
s3p80c5/c80c5/c80c8 address spaces 2- 13 common working register area (c0h?cfh) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 ? c0h?c7h rp1 ? c8h?cfh this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. register a hardware reset, register pointers rp0 and rp1 point to the commom working register area, locations c0h-cfh. rp0 = 1 1 0 0 0 0 0 0 rp1 = 1 1 0 0 1 0 0 0 ffh c0h bfh set 2 00h prime area set 1 ffh cfh c0h fch e0h dfh page 0 ~ ~ figure 2-10. common working register area
address spaces s3p 80c5/c80c5/c80c8 2- 14 f f programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example 1: ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h example 2: add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of the register pointers ("0" selects rp0; "1" selects rp1); ? the five high-order bits in the register pointer select an 8-byte slice of the register space; ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing: the high-order bit of the instruction 'inc r6' is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
s3p80c5/c80c5/c80c8 address spaces 2- 15 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address provides three low-order bits figure 2-11. 4-bit working register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction: 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-12. 4-bit working register addressing example
address spaces s3p 80c5/c80c5/c80c8 2- 16 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100b. this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing: the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bit 4 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit logical address 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low- order bits these address bits indicate 8-bit working register addressing 1 1 0 0 figure 2-13. 8-bit working register addressing
s3p80c5/c80c5/c80c8 address spaces 2- 17 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing register address (0abh) figure 2-14. 8-bit working register addressing example
address spaces s3p 80c5/c80c5/c80c8 2- 18 system and user stacks s3c8-series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3p80c5/c80c5/c80c8 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address value is always decreased by one before a push operation and increased by one after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-15. stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl) register location d9h contain the 8-bit stack pointer (spl) that is used for system stack operations. after a reset, the spl value is undetermined. because only internal memory 256-byte is implemented in s3p80c5/c80c5/c80c8, the spl must be initialized to an 8-bit value in the range 00h?ffh.
s3p80c5/c80c5/c80c8 address spaces 2- 19 f f programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ? ffh ; (normally, the spl is set to 0ffh by the initialization ; rout ine) ? ? ? push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 ? ? ? pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
address spaces s3p 80c5/c80c5/c80c8 2- 20 notes
s3p80c5/c80c5/c80c8 addressing modes 3- 1 3 addressing modes overview the program counter is used to fetch instructions that are stored in program memory for execution. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c8-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3p80c5/c80c 5/c80c8 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing because it uses a register pointer to specify an 8- byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address register file program memory figure 3-1. register addressing 4-bit working register points to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file 3 lsbs rp0 or rp1 selected rp points to start of working register block msb points to rp0 ot rp1 dst opcode src operand figure 3-2. working register addressing
s3p80c5/c80c5/c80c8 addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space, if implemented (see figures 3-3 through 3-6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. remember, however, that locations c0h?ffh in set 1 cannot be accessed using indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address. program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes s3p80c5/c80c 5/c80c8 3- 4 indirect register addressing mode (c ontinued) dst opcode points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register pair program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
s3p80c5/c80c5/c80c8 addressing modes 3- 5 indirect register addressing mode (c ontinued) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs selected rp points to start of woking register block rp0 or rp1 msb points to rp0 or rp1 ~ ~ ~ ~ value used in instruction operand figure 3-5. indirect working register addressing to register file
addressing modes s3p80c5/c80c 5/c80c8 3- 6 indirect register addressing mode (c ontinued) dst opcode 4-bit working register address sample instructions: ldc r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block note: lde command is not available, because an external interface is not implemented for the S3C80C5/c80c8/c80c4. figure 3-6. indirect working register addressing to program or data memory
s3p80c5/c80c5/c80c8 addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory (if implemented). you cannot, however, access locations c0h?ffh in set 1 using indexed addressing. in short offset indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8). for register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory (if implemented). dst/src opcode two-operand instruction example point to one of the working register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~ ~ ~ ~ + msb points to rp0 or rp1 figure 3-7. indexed addressing to register file
addressing modes s3p80c5/c80c 5/c80c8 3- 8 indexed addressing mode (c ontinued) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4 bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8 bits 16 bits 16 bits + ~ ~ note: lde command is not available, because an external interface is not implemented for the S3C80C5/c80c8/c80c4. figure 3-8. indexed addressing to program or data memory with short offset
s3p80c5/c80c5/c80c8 addressing modes 3- 9 indexed addressing mode (c ontinued) register file operand program memory or data memory point to working register pair lsb selects 16 bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits dst/src opcode program memory x offset 4 bit working register address offset + ~ ~ note: lde command is not available, because an external interface is not implemented for the S3C80C5/c80c8/c80c4. figure 3-9. indexed addressing to program or data memory
addressing modes s3p80c5/c80c 5/c80c8 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory note: lde command is not available, because an external interface is not implemented for the S3C80C5/c80c8/c804c. figure 3-10. direct addressing for load instructions
s3p80c5/c80c5/c80c8 addressing modes 3- 11 direct address mode (c ontinued) opcode program memory lower address byte program memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16 bit immediate address call display ; where display is a 16 bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3p80c5/c80c 5/c80c8 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16 bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing
s3p80c5/c80c5/c80c8 addressing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing
addressing modes s3p80c5/c80c 5/c80c8 3- 14 immediate mode (im) in immediate (im) mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
s3p80c5/c80c5/c80c8 control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3p80c5/c80c5/c80c8 control registers are presented in an easy-to- read format. you can use this section as a quick-reference source when writing application programs. figure 4-1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. data and counter registers are not described in detail in this reference section. more information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in part ii of this manual.
control registers s3p80c5/c80c5 /c80c8 4- 2 table 4-1. mapped registers (set 1) register name mnemonic decimal hex r/w timer 0 counter t0cnt 208 d0h r (note) timer 0 data register t0data 209 d1h r/w timer 0 control register t0con 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w locations d8h is not mapped. stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r (note) interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w location e3h?e6h is not mapped. port 0 pull-up resistor enable register p0pur 231 e7h r/w port 0 control register (high byte) p0conh 232 e8h r/w port 0 control register (low byte) p0conl 233 e9h r/w port 1 control register (high byte) p1conh 234 eah r/w port 1 control register (low byte) p1conl 235 ebh r/w port 1 pull-up resistor enable register p1pur 236 ech r/w location edh?efh is not mapped. port 2 control register p2con 239 f0h r/w port 0 interrupt enable register p0int 241 f1h r/w port 0 interrupt pending register p0pnd 242 f2h r/w counter a control register cacon 243 f3h r/w counter a data register (high byte) cadatah 244 f4h r/w counter a data register (low byte) cadatal 245 f5h r/w timer 1 counter register (high byte) t1cnth 246 f6h r (note) timer 1 counter register (low byte) t1cntl 247 f7h r (note) timer 1 data register (high byte) t1datah 248 f8h r/w
s3p80c5/c80c5/c80c8 control registers 4- 3 table 4-1. mapped registers (continued) register name mnemonic decimal hex r/w timer 1 data register (low byte) t1datal 249 f9h r/w timer 1 control register t1con 250 fah r/w stop control register stopcon 251 fbh w locations fch is not mapped. basic timer counter btcnt 253 fdh r (note) external memory timing register emt 254 feh r/w interrupt priority register ipr 255 ffh r/w note : you cannot use a read-only register as a destination for the instructions or, and, ld, or ldb.
control registers s3p80c5/c80c5 /c80c8 4- 4 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used addressing mode or modes you can use to modify register values reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x x x r/w r/w r/w register addressing mode only .4 .3 .2 .1 .0 x r/w x r/w x r/w x r/w 0 r/w bit number: msb = bit 7 lsb = bit 0 figure 4-1. register description format
s3p80c5/c80c5/c80c8 control registers 4- 5 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit addressing register addressing mode only .7?.4 watchdog timer function disable code (for system reset) 1 0 1 0 disable watchdog timer function any other value enable watchdog timer function .3?.2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting; not used for s3p80c5/c80c5/c80c8. .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer and timer 0 (2) 0 no effect 1 clear both clock frequency dividers notes : 1. when you write a "1" to btcon.1, the basic timer counter value is cleared to '00h'. immediately following the write operation, the btcon.1 value is automatically cleared to "0". 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to '00h'. immediately following the write operation, the btcon.0 value is automatically cleared to "0".
control registers s3p80c5/c80c5 /c80c8 4- 6 cacon ? counter a control register f3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 counter a input clock selection bits 0 0 f osc 0 1 f osc /2 1 0 f osc /4 1 1 f osc /8 .5?.4 counter a interrupt timing selection bits 0 0 elapsed time for low data value 0 1 elapsed time for high data value 1 0 elapsed time for combined low and high data values 1 1 invalid setting; not used for S3C80C5/c80c8. .3 counter a interrupt enable bit 0 disable interrupt 1 enable interrupt .2 counter a start bit 0 stop counter a 1 start counter a .1 counter a mode selection bit 0 one-shot mode 1 repeating mode .0 counter a output flip-flop control bit 0 flip-flop low level (t-ff = low) 1 flip-flop high level (t-ff = high)
s3p80c5/c80c5/c80c8 control registers 4- 7 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 oscillator irq wake-up function enable bit not used for s3p80c5/c80c5/c80c8. .6?.5 main oscillator stop control bits not used for s3p80c5/c80c5/c80c8. .4?.3 cpu clock (system clock) selection bits (1) 0 0 f osc /16 0 1 f osc /8 1 0 f osc /2 1 1 f osc (non-divided) .2?.0 subsystem clock selection bit (2) 1 0 1 invalid setting for s3p80c5/c80c5/c80c8. other value select main system clock (mclk) notes : 1. after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, loa d the appropriate values to clkcon.3 and clkcon.4. 2. these selection bits are required only for systems that have a main clock and a subsystem clock. the s3p80c5/c80c5/c80c8 uses only the main oscillator clock circuit. for this reason, the setting '101b' is invalid.
control registers s3p80c5/c80c5 /c80c8 4- 8 emt ? external memory timing register (note) feh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 1 1 1 1 1 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7 external wait wait input function enable bit 0 disable wait input function for external device 1 enable wait input function for external device .6 slow memory timing enable bit 0 disable wait input function for external device 1 enable wait input function for external device .5?.4 program memory automatic wait control bits 0 0 no wait 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .3?.2 data memory automatic wait control bits 0 0 no wait 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .1 stack area selection bit 0 select internal register file area 1 select external data memory area .0 not used for s3p80c5/c80c5/c80c8. note : the emt register is not used for s3p80c5/c80c5/c80c8, because an external peripheral interface is not implemented in the s3p80c5/c80c5/c80c8. the program initialization routine should clear the emt register to '00h' following a reset. modification of emt values during normal operation may cause a system malfunction.
s3p80c5/c80c5/c80c8 control registers 4- 9 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 interrupt return (iret) in progress (when read) 1 fast interrupt service routine in progress (when read) .0 bank address selection flag (ba) 0 bank 0 is selected (normal setting for S3C80C5/c80c8) 1 invalid selection (bank 1 is not implemented)
control registers s3p80c5/c80c5 /c80c8 4- 10 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt level 7 (irq7) enable bit; external interrupts p0.7?p0.4 1 enable ( un-mask) .6 interrupt level 6 (irq6) enable bit; external interrupts p0.3?p0.0 0 disable (mask) 1 enable ( un-mask) .5 not used for s3p80c5/c80c5/c80c8. .4 interrupt level 4 (irq4) enable bit; counter a interrupt 0 disable (mask) 1 enable ( un-mask) .3?.2 not used for s3p80c5/c80c5/c80c8. .1 interrupt level 1 (irq1) enable bit; timer 1 match or overflow 0 disable (mask) 1 enable ( un-mask) .0 interrupt level 0 (irq0) enable bit; timer 0 match or overflow 0 disable (mask) 1 enable ( un-mask) notes: 1. when an interrupt level is masked, any interrupt requests that may be issued are not recognized by the cpu. 2. interrupt levels irq2, irq3 and irq5 are not used in the s3p80c5/c80c5/c80c8 interrupt structure.
s3p80c5/c80c5/c80c8 control registers 4- 11 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah).
control registers s3p80c5/c80c5 /c80c8 4- 12 ipr ? interrupt priority register ffh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit addressing register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5, .3 not used for s3p80c5/c80c5/c80c8. .2 input group b priority control bit 0 irq4 1 irq4 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 note : the s3p80c5/c80c5/c80c8 interrupt structure uses only five levels: irq0, irq1, irq4, irq6?ir q7. because irq2, irq3, irq5 are not recognized, the interrupt subgroup b and group c settings (ipr.2,.3 and ipr.5) are not evaluated.
s3p80c5/c80c5/c80c8 control registers 4- 13 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only .7 level 7 (irq7) request pending bit; external interrupts p0.7?p0.4 0 not pending 1 pending .6 level 6 (irq6) request pending bit; external interrupts p0.3?p0.0 0 not pending 1 pending .5 not used for s3p80c5/c80c5/c80c8. .4 level 4 (irq4) request pending bit; counter a interrupt 0 not pending 1 pending .3?.2 not used for s3p80c5/c80c5/c80c8. .1 level 1 (irq1) request pending bit; timer 1 match or overflow 0 not pending 1 pending .0 level 0 (irq0) request pending bit; timer 0 match or overflow 0 not pending 1 pending note : interrupt level irq2, irq3 and irq5 is not used in the s3p80c5/c80c5/c80c8 interrupt structure.
control registers s3p80c5/c80c5 /c80c8 4- 14 p0conh ? port 0 control register (high byte) e8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p0.7/int4 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .5?.4 p0.6/int4 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .3?.2 p0.5/int4 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .1?.0 p0.4/int4 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges notes : 1. the int4 external interrupts at the p0.7?p0.4 pins share the same interrupt level (irq7) and interrupt vector address (e8h). 2. you can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the p0pur register.
s3p80c5/c80c5/c80c8 control registers 4- 15 p0conl ? port 0 control register (low byte) e9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p0.3/int3 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .5?.4 p0.2/int2 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .3?.2 p0.1/int1 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges .1?.0 p0.0/int0 mode selection bits 0 0 c-mos input mode; interrupt on falling edges 0 1 c-mos input mode; interrupt on rising and falling edges 1 0 push-pull output mode 1 1 c-mos input mode; interrupt on rising edges notes : 1. the int3?int0 external inte rrupts at p0.3?p0.0 are interrupt level irq6. each interrupt has a separate vector address. 2. you can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the p0pur register.
control registers s3p80c5/c80c5 /c80c8 4- 16 p0int ? port 0 external interrupt enable register f1h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only .7 p0.7 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .6 p0.6 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .5 p0.5 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .4 p0.4 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .3 p0.3 external interrupt (int3) enable bit 0 disable interrupt 1 enable interrupt .2 p0.2 external interrupt (int2) enable bit 0 disable interrupt 1 enable interrupt .1 p0.1 external interrupt (int1) enable bit 0 disable interrupt 1 enable interrupt .0 p0.0 external interrupt (int0) enable bit 0 disable interrupt 1 enable interrupt
s3p80c5/c80c5/c80c8 control registers 4- 17 p0pnd ? port 0 external interrupt pending register f2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p0.7 external interrupt (int4) pending flag (note) 0 no p0.7 external interrupt pending (when read) 1 p0.7 external interrupt is pending (when read) .6 p0.6 external interrupt (int4) pending flag 0 no p0.6 external interrupt pending (when read) 1 p0.6 external interrupt is pending (when read) .5 p0.5 external interrupt (int4) pending flag 0 no p0.5 external interrupt pending (when read) 1 p0.5 external interrupt is pending (when read) .4 p0.4 external interrupt (int4) pending flag 0 no p0.4 external interrupt pending (when read) 1 p0.4 external interrupt is pending (when read) .3 p0.3 external interrupt (int3) pending flag 0 no p0.3 external interrupt pending (when read) 1 p0.3 external interrupt is pending (when read) .2 p0.2 external interrupt (int2) pending flag 0 no p0.2 external interrupt pending (when read) 1 p0.2 external interrupt is pending (when read) .1 p0.1 external interrupt (int1) pending flag 0 no p0.1 external interrupt pending (when read) 1 p0.1 external interrupt is pending (when read) .0 p0.0 external interrupt (int0) pending flag 0 no p0.0 external interrupt pending (when read) 1 p0.0 external interrupt is pending (when read) note : to clear an interrupt pending condition, write a "0" to the appropriate pending flag. writing a "1" to an interrupt pending flag (pond.0?7) has no effect.
control registers s3p80c5/c80c5 /c80c8 4- 18 p0pur ? port 0 pull-up resistor enable register e7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p0.7 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .6 p0.6 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .5 p0.5 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .4 p0.4 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .3 p0.3 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .2 p0.2 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .1 p0.1 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor .0 p0.0 pull-up resistor enable bit 0 enable pull-up resistor 1 disable pull-up resistor
s3p80c5/c80c5/c80c8 control registers 4- 19 p1conh ? port 1 control register (high byte) eah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p1.7 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .5?.4 p1.6 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .3?.2 p1.5 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .1?.0 p1.4 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting
control registers s3p80c5/c80c5 /c80c8 4- 20 p1conl ? port 1 control register (low byte) ebh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p1.3 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .5?.4 p1.2 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .3?.2 p1.1 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting .1?.0 p1.0 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 invalid setting
s3p80c5/c80c5/c80c8 control registers 4- 21 p1pur ? port 0 pull-up resistor enable register ech set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p1.7 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .6 p1.6 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .5 p1.5 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .4 p1.4 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .3 p1.3 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 p1.2 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 p1.1 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 p1.0 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor
control registers s3p80c5/c80c5 /c80c8 4- 22 p2con ? port 2 control register f0h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p2.2 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 c-mos input with pull up mode .5?.4 p2.1 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 c-mos input with pull up mode .3?.2 p2.0 mode selection bits 0 0 c-mos input mode 0 1 open-drain output mode 1 0 push-pull output mode 1 1 c-mos input with pull up mode .1 p2.1 alternative function selection bits 0 normal i/o function 0 rem/t0ck function .0 p2.0 alternative function selection bits 0 normal i/o function 0 t0pwn function
s3p80c5/c80c5/c80c8 control registers 4- 23 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 destination register page selection bits 0 0 0 0 destination: page 0 (note) .3?.0 source register page selection bits bits 0 0 0 0 source: page 0 (note) note : in the s3p80c5/c80c5/c80c8 microcontroller, a paged expansion of the internal register file is not implemented. for this reason, only page 0 settings are valid. register page point er values for the source and destination register page are automatically set to '0000b' following a hardware reset. these values should not be changed during normal operation.
control registers s3p80c5/c80c5 /c80c8 4- 24 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing mode only .7?.3 destination register page selection bits register pointer 0 can independently point to one of the 24 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h?c7h. .2?.0 not used for s3p80c5/c80c5/c80c8. rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing mode only .7?.3 register pointer 1 address value register pointer 1 can independently point to one of the 24 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2?.0 not used for s3p80c5/c80c5/c80c8.
s3p80c5/c80c5/c80c8 control registers 4- 25 spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (low byte) the sp value is undefined following a reset. stopcon ? stop control register fbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w addressing mode register addressing mode only .7?.0 stop control register enable bits 1 0 1 0 0 1 0 1 enable stopcon notes : 1. to get into stop mode , stop control register must be enabled just before stop instruction. 2. when stop mode is released, stop control register (stopcon) value is cleared automatically. 3. it is prohibited to write another value into stopcon.
control registers s3p80c5/c80c5 /c80c8 4- 26 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 tri-state external interface control bit (1) 0 normal operation (disable tri-state operation) 1 set external interface lines to high impedance (enable tri-state operation) .6?.5 not used for s3p80c5/c80c5/c80c8. .4?.2 fast interrupt level selection bits (2) 0 0 0 irq0 0 0 1 irq1 0 1 0 not used for 0 1 1 s3p80c5/c80c5/c80c8. 1 0 0 1 0 1 1 1 0 irq6 1 1 1 irq7 .1 fast interrupt enable bit (3) 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit (4) 0 disable global interrupt processing 1 enable global interrupt processing notes : 1. because an external interface is not implemented for the s3p80c5/c80c5/c80c8, sym.7 must always be "0". 2. you can select only one interrupt level at a time for fast interrupt processing. 3. setting sym.1 to "1" enables fast interrupt processing for the interrupt level currently selected by sym.2?sym.4. 4. following a reset, you must enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
s3p80c5/c80c5/c80c8 control registers 4- 27 t0con ? timer 0 control register d2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer 0 input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc /8 1 1 external clock input (at the t0ck pin, p2.1) .5?.4 timer 0 operating mode selection bits 0 0 interval timer mode (counter cleared by match signal) 0 1 overflow mode (ovf interrupt can occur) 1 0 overflow mode (ovf interrupt can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer 0 counter clear bit 0 no effect (when write) 1 clear t0 counter, t0cnt (when write) .2 timer 0 overflow interrupt enable bit (note) 0 disable t0 overflow interrupt 1 enable t0 overflow interrupt .1 timer 0 match interrupt enable bit 0 disable t0 match interrupt 1 enable t0 match interrupt .0 timer 0 match interrupt pending flag 0 no t0 match interrupt pending (when read) 0 clear t0 match interrupt pending condition (when write) 1 t0 match interrupt is pending (when read) 1 no effect (when write) note : a timer 0 overflow interrupt pending condition is automatically cleared by hardware. however, the timer 0 match/ capture interrupt, irq0, vector fch, must be cleared by the interrupt service routine.
control registers s3p80c5/c80c5 /c80c8 4- 28 t1con ? timer 1 control register fah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer 1 input clock selection bits 0 0 f osc /4 0 1 f osc /8 1 0 f osc /16 1 1 internal clock (counter a flip-flop, t-ff) .5?.4 timer 1 operating mode selection bits 0 0 interval timer mode (counter cleared by match signal) 0 1 overflow mode (ovf interrupt can occur) 1 0 overflow mode (ovf interrupt can occur) 1 1 overflow mode (ovf interrupt can occur) .3 timer 1 counter clear bit 0 no effect (when write) 1 clear t1 counter, t1cnt (when write) .2 timer 1 overflow interrupt enable bit (note) 0 disable t1 overflow interrupt 1 enable t1 overflow interrupt .1 timer 1 match/capture interrupt enable bit 0 disable t1 match interrupt 1 enable t1 match interrupt .0 timer 1 match/capture interrupt pending flag 0 no t1 match interrupt pending (when read) 0 clear t1 match interrupt pending condition (when write) 1 t1 match interrupt is pending (when read) 1 no effect (when write) note : a timer 1 overflow interrupt pending condition is automatically cleared by hardware. however, the timer 1 match/ cap ture interrupt, irq1, vector f6h, must be cleared by the interrupt service routine.
s3p80c5/c80c5/c80c8 interrupt structure 5- 1 5 interrupt structure overview the s3c8-series interrupt structure has three basic components: levels, vectors, and sources. the sam87 cpu recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. a vector address can be assigned to one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight possible interrupt levels: irq0?irq7, also called level 0 ? level 7. each interrupt level directly corresponds to an interrupt request number ( irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. the s3p80c5/c80c5/c80c8 interrupt structure recognizes five interrupt levels. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are simply identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128. (the actual number of vectors used for s3c8-series devices is always much smaller.) if an interrupt level has more than one vector address, the vector priorities are set in hardware. the s3p80c5/c80c5/c80c8 uses ten vectors. one vector address is shared by four interrupt sources. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow, for example. each vector can have several interrupt sources. in the s3p80c5/c80c5/c80c8 interrupt structure, there are thirteen possible interrupt sources. when a service routine starts, the respective pending bit is either cleared automatically by hardware or is must be cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method is used to clear its respective pending bit.
interrupt structure s3p80c5/c80c5/c80c8 5- 2 interrupt types the three components of the s3c8 interrupt structure described above ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level ( irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level ( irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level ( irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3p80c5/c80c5/c80c8 microcontroller, all three interrupt types are implemented. vectors sources levels s 1 v 1 s 2 type 2: irqn s 3 s n v 1 s 1 v 2 s 2 type 3: irqn v 3 s 3 v 1 s 1 type 1: irqn v n s n + 1 s n s n + 2 s n + m notes: 1. the number of s n and v n value is expandable. 2. in the s3p80c5/c80c5/c80c8 implementation, interrupt types 1, 2, and 3 is used. figure 5-1. s3c8-series interrupt types
s3p80c5/c80c5/c80c8 interrupt structure 5- 3 s3p80c5/c80c5/c80c8 interrupt structure the s3p80c5 microcontroller supports two kinds interrupt structure ? vectored interrupt ? non vectored interrupt (reset interrupt): intr the s3p80c5/c80c5/c80c8 microcontroller supports thirteen interrupt sources. nine of the interrupt sources have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector address. five interrupt levels are recognized by the cpu in this device-specific interrupt structure, as shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. (the relative priorities of multiple interrupts within a single level are fixed in hardware.) when the cpu grants an interrupt request, interrupt processing starts: all other interrupts are disabled and the program counter value and state flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. the s3p80c5/c80c5/c80c8 microcontroller supports non vectored interrupt - interrupt with reset(intr) - to occur interrupt with system reset. the interrupt with reset(intr) has nothing to do with interrupt levels, vectors and the registers that are related to interrupt setting. it occurs only according to the ?p0? during ? stop ? regardless any other things. namely, only when a falling/rising edge occurs at any pin of port 0 during stop status, this intr and a system reset occurs even though sym.0 is ?0?(disable interrupt). but it dose not occurs while the oscillation - ?idle? or ?operating? status- even though a falling/rising edge occurs at port 0. following is the sequence that occurs interrupt with reset(intr). 1. the oscillation status is ?freeze? : stop mode 2. a falling/rising edge is detec ted to any pin of port 0. 3. intr occurs and it makes system reset. 4. stop mode is released by this system reset. note because h/w reset occurs whenever intr occurs. a user should aware of the each ports, system register, control register etc.?
interrupt structure s3p80c5/c80c5/c80c8 5- 4 note: for interrupt levels with two or more vectors, the lowest vector address usually the highest priority. for example, fah has the higher priority (0) than fch (1) within level irq0. these priorities are fixed in hardware. vectors sources levels reset/clear reset 100h basic timer overflow/intr/por h/w timer 0 match s/w irq0 timer 0 overflow h/w timer 1 match s/w irq1 timer 1 overflow h/w counter a h/w p0.3 external interrupt s/w p0.2 external interrupt s/w p0.1 external interrupt s/w p0.0 external interrupt s/w p0.7 external interrupt s/w p0.6 external interrupt s/w irq7 p0.5 external interrupt s/w p0.4 external interrupt s/w fch fah f6h f4h e8h e6h e4h irq6 e2h e0h irq4 ech 1 0 1 0 3 2 1 0 figure 5-2. s3p80c5/c80c5/c80c8 interrupt structure
s3p80c5/c80c5/c80c8 interrupt structure 5- 5 interrupt vector addresses all interrupt vector addresses for the s3p80c5/c80c5/c80c8 interrupt structure are stored in the vector address area of the internal program memory rom, 00h?ffh. you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses. (table 5-2 lists all vector addresses.) the program reset address in the rom is 0100h. 15,872 15-kbyte rom 8-kbyte rom interrupt vector area 8,191 255 0 3e00h 1fffh 0ffh 0h (decimal) (hex) S3C80C5 s3c80c8 figure 5-3. rom vector address area
interrupt structure s3p80c5/c80c5/c80c8 5- 6 table 5-1. s3p80c5/c80c5/c80c8 interrupt vectors vector address interrupt source request reset/clear decimal value hex value interrupt level priority in level h/w s/w 254 100h basic timer overflow reset ? ? 252 fch timer 0 (match) irq0 1 ? 250 fah timer 0 overflow 0 ? 246 f6h timer 1 (match) irq1 1 ? 244 f4h timer 1 overflow 0 ? 236 ech counter a irq4 ? ? 232 e8h p0.7 external interrupt irq7 ? ? 232 e8h p0.6 external interrupt ? ? 232 e8h p0.5 external interrupt ? ? 232 e8h p0.4 external interrupt ? ? 230 e6h p0.3 external interrupt irq6 3 ? 228 e4h p0.2 external interrupt 2 ? 226 e2h p0.1 external interrupt 1 ? 224 e0h p0.0 external interrupt 0 ? notes : 1. interrupt priorities are identified in inverse order: '0' i s highest priority, '1' is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. the priorities within a given level are fixed in hardware.
s3p80c5/c80c5/c80c8 interrupt structure 5- 7 enable/disable interrupt instructions (ei, di) executing the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are then serviced as they occur, and according to the established priorities. note the system initialization routine that is executed following a reset must always contain an ei instruction to globally enable the interrupt structure. during normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. although you can manipulate sym.0 directly to enable or disable interrupts, we recommend that you use the ei and di instructions instead. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables ( un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative priorities of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode registe r, sym, enables or disables global interrupt processing (sym settings also enable fast interrupts and control the activity of external interface, if implemented). table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the five interrupt levels: irq0, irq1, irq4, and irq6?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the five levels of the s3p80c5/c80c5/c80c8 are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq4, and group c is irq6, and irq7. interrupt request register irq r this register contains a request pending bit for each interrupt level. system mode register sym r/w dynamic global interrupt processing enable/ disable, fast interrupt processing, and external interface control (an external memory interface is not implemented in the s3p80c5/c80c5/c80c8 microcontroller).
interrupt structure s3p80c5/c80c5/c80c8 5- 8 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. the system-level control points in the interrupt structure are, therefore: ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0 ) ? interrupt level enable/disable settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corre sponding peripheral control registers note when writing the part of your application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. irq0, irq1, irq4 and irq6- irq7 interrupts ei interrupt request register (read-only) polling cycle interrupt mask register s r q reset interrupt priority register vector interrupt cycle global interrupt control (ei, di, or sym.0 manipulation) figure 5-4. interrupt function diagram
s3p80c5/c80c5/c80c8 interrupt structure 5- 9 peripheral interrupt control registers for each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (see table 5-3). table 5-3. interrupt source control and data registers interrupt source interrupt level register(s) location(s) in set 1 timer 0 match or timer 0 overflow irq0 t0con (note) t0data d2h d1h timer 1 match or timer 1 overflow irq1 t1con (note) t1datah, t1datal fah f8h, f9h counter a irq4 cacon cadatah, cadatal f3h f4h, f5h p0.7 external interrupt p0.6 external interrupt p0.5 external interrupt p0.4 external interrupt irq7 p0conh p0int p0pnd e8h f1h f2h p0.3 external interrupt p0.2 external interrupt p0.1 external interrupt p0.0 external interrupt irq6 p0conl p0int p0pnd e9h f1h f2h note : because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the t0con and t1con registers control only the enable/disable functions. the t0con and t1con registers contain enable/disable and pending bits for the timer 0 and timer 1 match interrupts, respectively.
interrupt structure s3p80c5/c80c5/c80c8 5- 10 system mode register (sym) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see figure 5-5). a reset clears sym.7, sym.1, and sym.0 to "0". the 3-bit value for fast interrupt level selection, sym.4?sym.2, is undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. although you can manipulate sym.0 directly to enable and disable interrupts during normal operation, we recommend using the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w global interrupt enable bit: 0 = disable all interrupts 1 = enable all interrupts not used for the S3C80C5/c80c8. external interface tri-state enable bit: 0 = normal (tri-state) 1 = high (tri-state) fast interrupt enable bit: 0 = disable fast interrupt 1 = enable fast interrupt fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 not used not used not used not used irq6 irq7 note: an external memory interface is not implemented. msb lsb .5 .7 .6 .4 .3 .2 .1 .0 figure 5-5. system mode register (sym)
s3p80c5/c80c5/c80c8 interrupt structure 5- 11 interrupt mask register (imr) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh, set 1, r/w irq0 irq1 not used not used irq4 not used irq6 irq7 interrupt level enable bits (7-6, 4, 1, 0): 0 = disable (mask) interrupt 1 = enable (un-mask) interrupt msb lsb .5 .7 .6 .4 .3 .2 .1 .0 figure 5-6. interrupt mask register (imr)
interrupt structure s3p80c5/c80c5/c80c8 5- 12 interrupt priority register (ipr) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels used in the microcontroller's interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt source is active, the source with the highest priority level is serviced first. if both sources belong to the same interrupt level, the source with the lowest vector address usually has priority (this priority is fixed in hardware). to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq4 group c irq6, irq7 ipr group b ipr group c irq4 irq6 c1 c2 irq7 ipr group a irq1 a2 irq0 a1 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting '001b' for these bits would select the group relationship b > c > a; the setting '101b' would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group b has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3, and 4. ipr.3 defines the possible subgroup b relationships. ipr.2 controls interrupt group b. in the s3p80c5/c80c5/c80c8 implementation, interrupt levels 2 and 3 are not used. therefore, ipr.2 and ipr.3 settings are not evaluated, as irq4 is the only remaining level in the group. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
s3p80c5/c80c5/c80c8 interrupt structure 5- 13 interrupt priority register (ipr) ffh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b (note) 0 = irq4 1 = irq4 group c (note) 0 = irq6, irq7 1 = irq6, irq7 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b (note) 0 = irq4 1 = irq4 group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = undefined = b > c > a = a > b > c = b > a > c = c > a > b = c > b > a = a > c > b = undefined d7 d4 d1 note: in this device interrupt structure, only levels irq0, irq1, irq4, irq6-irq7 are used. settings for group/subgroup b, which control relative priorities for levels irq2, irq3 and irq5, are therefore not evaluated. figure 5-8. interrupt priority register (ipr)
interrupt structure s3p80c5/c80c5/c80c8 5- 14 interrupt request register (irq) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level; a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to "0". you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch, set 1, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 not used not used irq4 not used irq6 irq7 irq0 interrupt level request pending bits: 0 = interrupt level is not pending 1 = interrupt level is pending figure 5-9. interrupt request register (irq)
s3p80c5/c80c5/c80c8 interrupt structure 5- 15 interrupt pending function types overview there are two types of interrupt pending bits: one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source by sending an iack, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the s3p80c5/c80c5/c80c8 interrupt structure, the timer 0 and timer 1 overflow interrupts (irq0 and irq1), and the counter a interrupt (irq4) belong to this category of interrupts whose pending condition is cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit must be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source's mode or control register. in the s3p80c5/c80c5/c80c8 interrupt structure, pending conditions for all interrupt sources except the timer 0 and timer 1 overflow interrupts and the counter a borrow interrupt, must be cleared by the interrupt service routine.
interrupt structure s3p80c5/c80c5/c80c8 5- 16 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's inte rrupt level. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr regi ster) ? the interrupt level must have the highest priority if more than one level is currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all sub sequent interrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags and sets sym.0 to "1", allowing the cpu to process the next interrupt request.
s3p80c5/c80c5/c80c8 interrupt structure 5- 17 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine specified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range 00h?ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher prior ity interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the above procedure to some extent. instruction pointer (ip) the instruction pointer (ip) is used by all s3c8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . the ip consists of register pair dah and dbh. the ip register names are iph (high byte, ip15?ip8) and ipl (low byte, ip7?ip0). fast interrupt processing the feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 16 clock cycles. to select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to sym.4?sym.2. then, to enable fast interrupt processing for the selected level, you set sym.1 to "1".
interrupt structure s3p80c5/c80c5/c80c8 5- 18 fast interrupt processing ( continued) two other system registers support fast interrupt processing: ? the instruction pointer (ip) contains the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' ("flags prime"). note for the s3p80c5/c80c5/c80c8 microcontroller, the service routine for any one of the five interrupt levels: irq0, irq1, irq4 or irq6?irq7, can be selected for fast interrupt processing. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer (ip). 2. load the interrupt level number ( irqn) into the fast interrupt selection field (sym.4?sym.2) 3. write a "1" to the fast interrupt enabl e bit in the sym register. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flag register values are written to the flags' ("flags prime") register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the ins truction pointer and pc values are swapped back. 6. the content of flags' ("flags prime") is copied automatically back to the flags register. 7. the fast interrupt status bit in flags is cleared automatically. relationship to interrupt pending bit types as described previously, there are two types of interrupt pending bits: one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed, and the other type must be cleared by the application program's interrupt service routine. you can select fast interrupt processing for interrupts with either type of pending condition clear function ? by hardware or by software. programming guidelines remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the sym register, sym.1. executing an ei or di instruction globally enables or disables all interrupt processing, including fast interrupts. if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends.
s3p80c5/c80c5/c80c8 instruction set 6- 1 6 instruction set overview the sam8 instruction set is specifically designed to support the large register files that are typical of most sam8 microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the sam8 cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes."
instruction set s3p80c5/c80c5/c80c8 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst, src load ldb dst, src load bit lde dst, src load external data memory ldc dst, src load program memory lded dst, src load external data memory and decrement ldcd dst, src load program memory and decrement ldei dst, src load external data memory and increment ldci dst, src load program memory and increment ldepd dst, src load external data memory with pre-decrement ldcpd dst, src load program memory with pre-decrement ldepi dst, src load external data memory with pre-increment ldcpi dst, src load program memory with pre-increment ldw dst, src load word pop dst pop from stack popud dst, src pop user stack ( decrementing) popui dst, src pop user stack (incrementing) push src push to stack pushud dst, src push user stack ( decrementing) pushui dst, src push user stack (incrementing)
s3p80c5/c80c5/c80c8 instruction set 6- 3 table 6-1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,src multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
instruction set s3p80c5/c80c5/c80c8 6- 4 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask
s3p80c5/c80c5/c80c8 instruction set 6- 5 table 6-1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
instruction set s3p80c5/c80c5/c80c8 6- 6 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, flags.7?flags.4, can be tested and used with conditional jump instructions; two others flags.3 and flags.2 are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb bank address status flag (ba) first interrupt status flag (fis) half-carry flag (h) decimal adjust flag (d) overflow (v) sign flag (s) zero flag (z) carry flag (c) figure 6-1. system flags register (flags)
s3p80c5/c80c5/c80c8 instruction set 6- 7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations, so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and cannot be used as a test condition. h half-carry flag (flags.2) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is seldom accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or b ank 1. the ba flag is cleared to "0" (select bank 0) when you execute the sb0 instruction and is set to "1" (select bank 1) when you execute the sb1 instruction.
instruction set s3p80c5/c80c5/c80c8 6- 8 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
s3p80c5/c80c5/c80c8 instruction set 6- 9 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn ( reg = 0?255, n = 0?15) rb bit 'b' of register or working register reg.b ( reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp ( reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr ( addr = 0?254, even number only) ir indirect working register only @ rn (n = 0?15) ir indirect register or indirect working register @ rn or @ reg ( reg = 0?255, n = 0?15) irr indirect working register pair only @ rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @ rrp or @ reg ( reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode # reg [ rn] ( reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode # addr [ rrp] ( addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode # addr [ rrp] ( addr = range 0?65535, where p = 0, 2, ..., 14) da direct addressing mode addr ( addr = range 0?65535) ra relative addressing mode addr ( addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = range 0?65535)
instruction set s3p80c5/c80c5/c80c8 6- 10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
s3p80c5/c80c5/c80c8 instruction set 6- 11 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop
instruction set s3p80c5/c80c5/c80c8 6- 12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (note) c carry c = 1 1111 (note) nc no carry c = 0 0110 (note) z zero z = 1 1110 (note) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (note) eq equal z = 1 1110 (note) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (note) uge unsigned greater than or equal c = 0 0111 (note) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicates condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add i nstruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
s3p80c5/c80c5/c80c8 instruction set 6- 13 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam8 instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
instruction set s3p80c5/c80c5/c80c8 6- 14 adc ? add with carry adc dst,src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
s3p80c5/c80c5/c80c8 instruction set 6- 15 add ? add add dst,src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source wo rking register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in register r1.
instruction set s3p80c5/c80c5/c80c8 6- 16 and ? logical and and dst,src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
s3p80c5/c80c5/c80c8 instruction set 6- 17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) ? dst(0) and src(b) or dst(b) ? dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1,01h.1 ? r1 = 06h, register 01h = 05h band 01h.1,r1 ? register 01h = 05h, r1 = 07h in the first example, source register 01h contains the value 05h (00000101b) and destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of register r1 (destination), leaving the value 06h (00000110b) in register r1.
instruction set s3p80c5/c80c5/c80c8 6- 18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 ? r1 = 07h, register 01h = 01h if destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
s3p80c5/c80c5/c80c8 instruction set 6- 19 bitc ? bit complement bitc dst.b operation: dst(b) ? not dst(b) this instruction complements the specified bit within the destination without affecting any other bits in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit addr ess 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 ? r1 = 05h if working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
instruction set s3p80c5/c80c5/c80c8 6- 20 bitr ? bit reset bitr dst.b operation: dst(b) ? 0 the bitr instruction clears the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 ? r1 = 05h if the value of working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
s3p80c5/c80c5/c80c8 instruction set 6- 21 bits ? bit set bits dst.b operation: dst(b) ? 1 the bits instruction sets the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 ? r1 = 0fh if working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
instruction set s3p80c5/c80c5/c80c8 6- 22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) ? dst(0) or src(b) or dst(b) ? dst(b) or src(0) the specified bit of the source (or the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instructio n formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 ? r1 = 07h, register 01h = 03h bor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 contains the value 07h (00000111b) and source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in working register r1. in the second example, destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in register 01h.
s3p80c5/c80c5/c80c8 instruction set 6- 23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip,r1.3 ? pc jumps to skip location if working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3p80c5/c80c5/c80c8 6- 24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip,r1.1 if working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3p80c5/c80c5/c80c8 instruction set 6- 25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) ? dst(0) xor src(b) or dst(b) ? dst(b) xor src(0) the specified bit of the source (or the destination) is logically exclusive- ored with bit zero (lsb) of the destination (or source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: c leared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 01h = 03h (00000011b): bxor r1,01h.1 ? r1 = 06h, register 01h = 03h bxor 01h.2,r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 has the value 07h (00000111b) and source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive- ors bit one of register 01h (source) with bit zero of r1 (destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of source register 01h is unaffected.
instruction set s3p80c5/c80c5/c80c8 6- 26 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h ? sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h ? sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040h contains 35h and program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
s3p80c5/c80c5/c80c8 instruction set 6- 27 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
instruction set s3p80c5/c80c5/c80c8 6- 28 clr ? clear clr dst operation: dst ? "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the de stination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3p80c5/c80c5/c80c8 instruction set 6- 29 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0 ". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second exam ple, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
instruction set s3p80c5/c80c5/c80c8 6- 30 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags destination working register r1 contains the value 02 h and source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in working register r3.
s3p80c5/c80c5/c80c8 instruction set 6- 31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst ? src = "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 c2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1,@r2,skip ? r2 = 04h, pc jumps to skip location in this example, working register r1 contains the value 02h, working register r2 the value 03h, and register 03 contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3p80c5/c80c5/c80c8 6- 32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst ? src "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 d2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip ? r2 = 04h, pc jumps to skip location working register r1 contains the value 02h, working register r2 (the source pointer ) the value 03h, and general register 03 the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non-equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3p80c5/c80c5/c80c8 instruction set 6- 33 da ? decimal adjust da dst operation: dst ? da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed. (the operation is undefined if the destination operand was not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: un affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir
instruction set s3p80c5/c80c5/c80c8 6- 34 da ? decimal adjust da (continued) example: given: working register r0 contains the value 15 (bcd), working register r1 contains 27 (bcd), and address 27h contains 46 (bcd): add r1,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = c, r1 ? 3ch da r1 ; r1 ? 3ch + 06 if addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 ? 31?0 leave the value 31 (bcd) in address 27h (@r1).
s3p80c5/c80c5/c80c8 instruction set 6- 35 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
instruction set s3p80c5/c80c5/c80c8 6- 36 decw ? decrement word decw dst operation: dst ? dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 ? r0 = 12h, r1 = 33h decw @r2 ? register 30h = 0fh, register 31h = 20h in the first example, destination register r0 contains the value 12h and register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, we recommend that you use decw as shown in the following example: loop: d ecw rr0 ld r2,r1 or r2,r0 jr nz,loop
s3p80c5/c80c5/c80c8 instruction set 6- 37 di ? disable interrupts di operation: sym (0) ? 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if t he value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing. before changing imr, interrupt pending and interrupt source control register, be sure di state.
instruction set s3p80c5/c80c5/c80c8 6- 38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) ? remainder dst (lower) ? quotient the destination operand (16 bits) is divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 3 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if divisor or quotient = "0"; cleared otherwise. s: set if msb of quotient = "1"; cleared otherwise. v: set i f quotient is 3 2 8 or if divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 26/10 94 rr r 26/10 95 rr ir 26/10 96 rr im note: execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 ? r0 = 03h, r1 = 40h div rr0,@r2 ? r0 = 03h, r1 = 20h div rr0,#20h ? r0 = 03h, r1 = 80h in the first example, destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
s3p80c5/c80c5/c80c8 instruction set 6- 39 djnz ? decrement and jump if non-zero djnz r,dst operation: r ? r ? 1 if r 1 0, pc ? pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to ?128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0, or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1,loop djnz is typically used to control a "loop" of instruct ions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label.
instruction set s3p80c5/c80c5/c80c8 6- 40 ei ? enable interrupts ei operation: sym (0) ? 1 an ei inst ruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
s3p80c5/c80c5/c80c8 instruction set 6- 41 enter ? enter enter operation: sp ? sp ? 2 @sp ? ip ip ? pc pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows one example of how to use an enter statement. 0050 ip 0022 sp 22 data address data 0040 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 0043 ip 0020 sp 20 21 22 iph ipl data address data 0110 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 00 50 stack stack 110 routine before after
instruction set s3p80c5/c80c5/c80c8 6- 42 exit ? exit exit operation: ip ? @sp sp ? sp + 2 pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 (internal stack) 2f 16 (internal stack) example: the diagram below shows one example of how to use an exit statement. 0050 ip 0022 sp address data 0040 pc address data memory 0052 ip 0022 sp address data 0060 pc address data memory stack stack before after 22 data 20 21 22 iph ipl data 00 50 50 51 140 pcl old pch exit 60 00 2f 60 main
s3p80c5/c80c5/c80c8 instruction set 6- 43 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
instruction set s3p80c5/c80c5/c80c8 6- 44 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set i f the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of register 1bh from 0fh to 10h.
s3p80c5/c80c5/c80c8 instruction set 6- 45 incw ? increment word incw dst operation: dst ? dst + 1 the contents of the desti nation (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0 fh, and register 03h = 0ffh: incw rr0 ? r0 = 1ah, r1 = 03h incw @r1 ? register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in register r0 and 02h in register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of general register 03h from 0ffh to 00h and register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, we recommend that you use incw as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop
instruction set s3p80c5/c80c5/c80c8 6- 46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags ? @sp pc ? ip sp ? sp + 1 flags ? flags' pc ? @sp fis ? 0 sp ? sp + 2 sym(0) ? 1 this instruction is used at the end of a n interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 10 (internal stack) bf 12 (internal stack) iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupts are enabled. when an interrupt occurs, the program counter and instruction pointer are swapped. this causes the pc to jump to address 100h and the ip to keep the return address. the last instruction in the service routine normally is a jump to iret at address ffh. this causes the instruction pointer to be loaded with 100h "again" and the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note: in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last two instructions. the iret cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the ipr register).
s3p80c5/c80c5/c80c8 instruction set 6- 47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,la bel_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the con tents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
instruction set s3p80c5/c80c5/c80c8 6- 48 jr ? jump relative jr cc,dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed. (see list of condition codes). the range of the relative ad dress is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry f lag is set (that is, if the condition code is true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3p80c5/c80c5/c80c8 instruction set 6- 49 ld ? load ld dst,src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
instruction set s3p80c5/c80c5/c80c8 6- 50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3p80c5/c80c5/c80c8 instruction set 6- 51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) ? src(b) or dst(b) ? src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note : in the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 ? r0 = 07h, register 00h = 05h ldb 00h.0,r0 ? r0 = 06h, register 00h = 04 h in the first example, destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of register r0 to the specified bit (bit zero) of the destination register, leaving 04h in general register 00h.
instruction set s3p80c5/c80c5/c80c8 6- 52 ldc/lde ? load memory ldc/lde dst,src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes ' irr' or ' rr' values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [ rr] 4. opc src | dst xs 3 12 f7 xs [ rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [ rr] 6. opc src | dst xl l xl h 4 14 b7 xl [ rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source ( src) or working register pair [ rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 and 4, the destination address 'xs [ rr]' and the source address 'xs [ rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [ rr] and the source address 'xl [ rr]' are each two bytes. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
s3p80c5/c80c5/c80c8 instruction set 6- 53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into progr am memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr2] ; r0 ? contents of program memory location 0105h ; (01h + rr2), ; r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 ? contents of external data memory location 0105h ; (01h + rr2), r0 = 7dh, r2 = 01h, r3 = 04h ldc (note) #01h[rr2],r0 ; 11 h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) ? 11h note: these instructions are not supported by masked rom type devices.
instruction set s3p80c5/c80c5/c80c8 6- 54 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst ? src rr ? rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes ' irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data m emory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
s3p80c5/c80c5/c80c8 instruction set 6- 55 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes ' irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; externa l data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
instruction set s3p80c5/c80c5/c80c8 6- 56 ldcpd/ldepd ? load memory with pre-decrement ldcpd/ ldepd dst,src operation: rr ? rr ? 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes ' irr' an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into program memory location ; 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh
s3p80c5/c80c5/c80c8 instruction set 6- 57 ldcpi/ldepi ? load memory with pre-increment ldcpi/ ldepi dst,src operation: rr ? rr + 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refer s to program memory and ldepi refers to external data memory. the assembler makes ' irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into program memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h
instruction set s3p80c5/c80c5/c80c8 6- 58 ldw ? load word ldw dst,src operation: dst ? src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h, and register 03h = 0fh: ldw rr6,rr4 ? r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h ? register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 ? r2 = 03h, r3 = 0fh, ldw 04h,@01h ? register 04h = 03h, register 05h = 0fh ldw rr6,#1234h ? r6 = 12h, r7 = 34h ldw 02h,#0fedh ? register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h, 03h into the destination word 00h, 01h. this leaves the value 03h in general register 00h and the value 0fh in register 01h. the other examples show how to use the ldw instruction with various addressing modes and formats.
s3p80c5/c80c5/c80c8 instruction set 6- 59 mult ? multiply (unsigned) mult dst,src operation: dst ? dst src the 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 22 84 rr r 22 85 rr ir 22 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h ? register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h ? register 00h = 00h, register 01h = 0c0h mult 00h, #30h ? register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h,02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16 -bit product, 0120h, is stored in the register pair 00h, 01h.
instruction set s3p80c5/c80c5/c80c8 6- 60 next ? next next operation: pc ? @ ip ip ? ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 0f example: the following diagram shows one example of how to use the next instruction. data 01 10 before after 0045 ip address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 ip address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
s3p80c5/c80c5/c80c8 instruction set 6- 61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
instruction set s3p80c5/c80c5/c80c8 6- 62 or ? logical or or dst,src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0,r1" logical- ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3p80c5/c80c5/c80c8 instruction set 6- 63 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h ? register 00h = 55h, sp = 00fch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 00fbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 00fch.
instruction set s3p80c5/c80c5/c80c8 6- 64 popud ? pop user stack ( decrementing) popud dst,src operation: dst ? src ir ? ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h ? register 00h = 41h, register 02h = 6fh, register 42h = 6fh if general register 00h contains the value 42h and register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of register 42h into the destination register 02h. the user stack pointer is then decremented by one, leaving the value 41h.
s3p80c5/c80c5/c80c8 instruction set 6- 65 popui ? pop user stack (incrementing) popui dst,src operation: dst ? src ir ? ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h ? register 00h = 02h, register 01h = 70h, register 02h = 70h if general register 00h contains the value 01h and register 01h the value 70h, the statement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (register 00h) is then incremented by one, changing its value from 01h to 02h.
instruction set s3p80c5/c80c5/c80c8 6- 66 push ? push to stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the source ( src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h ? register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of register 40h into location 0ffffh and adds this new value to the top of the stack.
s3p80c5/c80c5/c80c8 instruction set 6- 67 pushud ? push user stack ( decrementing) pushud dst,src operation: ir ? ir ? 1 dst ? src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h ? register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
instruction set s3p80c5/c80c5/c80c8 6- 68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ? ir + 1 dst ? src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h ? register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
s3p80c5/c80c5/c80c8 instruction set 6- 69 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
instruction set s3p80c5/c80c5/c80c8 6- 70 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 (internal stack) af 10 (internal stack) example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 00feh the statement "ret" pops the contents of stack poin ter location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 00feh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 00feh.
s3p80c5/c80c5/c80c8 instruction set 6- 71 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02 h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
instruction set s3p80c5/c80c5/c80c8 6- 72 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the conten ts of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3p80c5/c80c5/c80c8 instruction set 6- 73 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n ) ? dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: regist er 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
instruction set s3p80c5/c80c5/c80c8 6- 74 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3p80c5/c80c5/c80c8 instruction set 6- 75 sb0 ? select bank 0 sb0 operation: bank ? 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting bank 0 register addressing.
instruction set s3p80c5/c80c5/c80c8 6- 76 sb1 ? select bank 1 sb1 operation: bank ? 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (bank 1 is not implemented in some ks88-series microcontrollers.) flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to "1", selecting bank 1 register addressing, if implemented.
s3p80c5/c80c5/c80c8 instruction set 6- 77 sbc ? subtract with carry sbc dst,src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred ( src > dst); cleared otherwise. z: set if the result is "0"; cleared othe rwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in t he first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
instruction set s3p80c5/c80c5/c80c8 6- 78 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3p80c5/c80c5/c80c8 instruction set 6- 79 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 0 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: s et if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contain s the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
instruction set s3p80c5/c80c5/c80c8 6- 80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3?7) ? src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3? 7) ? src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4?7) ? src (4?7), rp0 (3) ? 0 rp1 (4?7) ? src (4?7), rp1 (3) ? 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets register pointer 0 (rp0) at location 0d6h to 40h and register pointer 1 (rp1) at location 0d7h to 48h. the statement "srp0 #50h" sets rp0 to 50h, and the statement "srp1 #68h" sets rp1 to 68h.
s3p80c5/c80c5/c80c8 instruction set 6- 81 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
instruction set s3p80c5/c80c5/c80c8 6- 82 sub ? subtract sub dst,src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 0 3h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
s3p80c5/c80c5/c80c8 instruction set 6- 83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h ? register 00h = 0e3h swap @02h ? register 02h = 03h, register 03h = 4ah in the first example, if general register 00h contains the value 3eh (00111110b), the statement "swap 00h" swaps the lower and upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
instruction set s3p80c5/c80c5/c80c8 6- 84 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if th e result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r 1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3p80c5/c80c5/c80c8 instruction set 6- 85 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
instruction set s3p80c5/c80c5/c80c8 6- 86 wfi ? wait for interrupt wfi operation: the cpu is effectively halted until an interrupt occurs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt . flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt)
s3p80c5/c80c5/c80c8 instruction set 6- 87 xor ? logical exclusive or xor dst,src operation: dst ? dst xor src the source operand is logically exclusive- ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 02h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive- ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
instruction set s3p80c5/c80c5/c80c8 6- 88 notes
s3p80c5/c80c5/c80c8 clock circui ts 7- 1 7 clock circuits overview the clock frequency generated for the s3p80c5/c80c5/c80c8 by an external crystal, or supplied by an external clock source, can range from 1mhz to 4 mhz. the maximum cpu clock frequency, as determined by clkcon register settings, is 4 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an external clock) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (f osc divided by 1, 2, 8, or 16) ? clock circuit control register, clkcon x in x out c1 c2 figure 7-1. main oscillator circuit (external crystal or ceramic resonator) x in x out external clock open pin figure 7-2. external clock circuit
clock circuits s3p80c5 /c80c5/c80c8 7- 2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by power on reset operation or by a non-vectored interrupt - interrupt with reset (intr). to enter the stop mode, stopcon (stop control register) has to be loaded with value, #0a5h before stop instruction execution. after recovering from the stop mode by reset or interrupt, stopcon register is automatically cleared. ? in idle mode, the internal clock signal is gated away from the cpu, but continues to be supplied to the interrupt structure, timer 0, and counter a. idle mode is released by a reset or by an interrupt (external or internally generated). main osc stop instruction noise filter oscillator stop oscillator wake-up int pin (1) 1/16 1/2 1/8 m u x clkcon.3,.4 stopcon cpu clock notes: 1. an external interrupt with an rc-delay noise filter (for S3C80C5/c80c8/, int0-4) is fiexed to release stop mode and "wake up" the main oscillator. 2. because the S3C80C5/c80c8 has no subsystem clock, the 3-bit clkcon signature code (clkcon.2-clkcon.0) is no meaning. figure 7-3. system clock circuit diagram
s3p80c5/c80c5/c80c8 clock circuits 7- 3 system clock control register (clkcon) the system clock control register, clkcon, is located in set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator frequency divide-by value clkcon register settings control whether or not an external interrupt can be used to trigger a stop mode release. (this is called the "irq wake-up" function.) the irq wake-up enable bit is clkcon.7. in s3p80c5/c80c5/c80c8, this bit is not valid any more. actually bit 7, 6, 5, 2, 1, and 0 are no meaning in s3p80c5/c80c5/c80c8. after a reset, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2, or f osc /8. system clock control register (clkcon) d4h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divide-by selection bits for cpu clock frequency: 00 = f osc /16 01 = f osc /8 10 = f osc /2 11 = f osc (non-divided) not used not used not used figure 7-4. system clock control register (clkcon)
clock circuits s3p80c5 /c80c5/c80c8 7- 4 notes
s3p80c5/c80c5/c80c8 reset reset and power-down 8- 1 8 reset reset and power-down system reset s3p80c5/c80c5/c80c8 has four different system reset sources as followings: ? low voltage detect (lvd) ? internal por circuit ? intr (interrupt with reset ) ? basic timer (watchdog timer) stopcon noise filter lvd stop intr por bt(wdt) enable/disable figure 8-1. reset block diagram lvd reset the low voltage detect circuit is built on the s3p80c5/c80c5/c80c8 product for system reset not in stop mode. when the operating status is not stop mode it detects a slope of v dd by comparing the voltage at v dd with v lvd (low level detect voltage). the reset pulse is generated by the rising slope of v dd . while the voltage at v dd is rising up and passing v lvd , the reset pulse is occurred at the moment ?v dd >= v lvd ". this function is disabled when the operating state is "stop mode" to reduce the current consumption under 1 ua instead of 6 ua.
reset reset and power-down s3p80c5/c80c5/c80c 8 8- 2 interrupt with reset(intr) a non vectored interrupt called interrupt with reset (intr) is built in S3C80C5/c80c8 to release stop status with system reset. when a falling/rising edge occurs at port 0 during stop mode, intr signal is generated and it makes the system reset pulse. an intr signal is generated relating to interaction between port 0 and operating status. it is enabled by stop status and occurs by falling/rising edge at port0. so only when the chip status is "stop", it is available. if the operating status is not stop status intr does not occurs. note this intr is supplementary function to make system reset for an application which is using " stop mode" like remote controller. if an application which is not using "stop mode" , intr function can be discarded. watchdog timer reset the s3p80c5/c80c5/c80c8 build a watch-dog timer that can recover to normal operation from abnormal function. watchdog timer generates a system reset signal if not clearing a bt-basic counter within a specific time by program. system reset can return to the proper operation of chip. power-on reset(por) the power-on reset circuit is built on the s3p80c5/c80c5/c80c8 product. during a power-on reset, the voltage at v dd goes to high level and the schmitt trigger input of por circuit is forced to low level and then to high level. the power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the schmitt trigger input senses the low level. this on-chip por circuit consists of an internal resistor, an internal capacitor, and a schmitt trigger input transistor. v dd system reset c r : on-chip resistor c : on-chip capacitor schmitt trigger inverter v ss figure 8-2. power-on reset circuit
s3p80c5/c80c5/c80c8 reset reset and power-down 8- 3 voltage [v] time reset pulse va reset pulse width v dd v ih = 0.85 v dd v il = 0.4 v dd t v dd (v dd rising time) v dd if va voltage is under the 0.4 v dd , reset pulse signal is gernerated. if va voltage is over than 0.4 vdd, reset pulse is not gernerated. figure 8 - 3 . timing diagram for power-on reset circuit system reset operation system reset starts the oscillation circuit, synchronize chip operation with cpu clock, and initialize the internal cpu and peripheral modules. this procedure brings the s3p80c5/c80c5/c80c8 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance. the minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks. all system and peripheral control registers are then reset to their default hardware values (see tables 5-1). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0, 1 and 2 are set to input mode and all pull-up resistors are disabled for the i/o port pin circuits. ? peripheral control and data register settings are disabled and reset to their default hardware values (see table 5-1). ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time int erval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed.
reset reset and power-down s3p80c5/c80c5/c80c 8 8- 4 hardware reset values tables 5-1 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined after a reset. ? a dash ('-') means that the b it is either not used or not mapped (but a 0 is read from the bit position) table 8-1. set 1 register values after reset register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 timer 0 counter (read-only) t0cnt 208 d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? location d8h (sph) is not mapped. stack pointer (low byte) spl 217 d9h instruction pointer (high byte) iph 218 dah instruction pointer (low byte) ipl 219 dbh interrupt request register (read-only) irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh system mode register sym 222 deh 0 ? ? 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 location e3h?e6h is not mapped. port 0 pull-up enable register p0pur 231 e7h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0conh 232 e8h 0 0 0 0 0 0 0 0 port 0 control register (low byte) p0conl 233 e9h 0 0 0 0 0 0 0 0
s3p80c5/c80c5/c80c8 reset reset and power-down 8- 5 table 8-1. set 1 register values after reset (continued) register name mnemonic address bit values after reset dec hex 7 6 5 4 3 2 1 0 port 1 control register (high byte) p1conh 234 eah 0 0 0 0 0 0 0 0 port 1 control register (low byte) p1conl 235 ebh 0 0 0 0 0 0 0 0 port 1 pull-up enable register p1pur 236 ech 0 0 0 0 0 0 0 0 location edh?efh is not mapped. port 2 control register p2con 240 f0h ? ? 0 0 0 0 0 0 port 0 interrupt enable register p0int 241 f1h 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd 242 f2h 0 0 0 0 0 0 0 0 counter a control register cacon 243 f3h 0 0 0 0 0 0 0 0 counter a data register (high byte) cadatah 244 f4h 1 1 1 1 1 1 1 1 counter a data register (low byte) cadatal 245 f5h 1 1 1 1 1 1 1 1 timer 1 counter register (high byte) t1cnth 246 f6h 0 0 0 0 0 0 0 0 timer 1 counter register (low byte) t1cntl 247 f7h 0 0 0 0 0 0 0 0 timer 1 data register (high byte) t1datah 248 f8h 1 1 1 1 1 1 1 1 timer 1 data register (low byte) t1datal 249 f9h 1 1 1 1 1 1 1 1 timer 1 control register t1con 250 fah 0 0 0 0 0 0 0 0 stop control register stopcon 251 fbh 0 0 0 0 0 0 0 0 locations fch is not mapped. basic timer counter btcnt 253 fdh external memory timing register emt 254 feh 0 1 1 1 1 1 0 ? interrupt priority register ipr 255 ffh notes: 1. although the sym register is not used for the s3p80c5/c80c5/c80c8 , sym.5 should always be "0". if you accidentally write a 1 to this bit during normal operation, a system malfunction may occur. 2. except for t0cnt, irq, t1cnth, t1cntl, and btcnt, which are read-only, all regi sters in set 1 are read/write addressable. 3. you cannot use a read-only register as a destination field for the instructions or, and, ld, and ldb. 4. interrupt pending flags are noted by shaded table cells.
reset reset and power-down s3p80c5/c80c5/c80c 8 8- 6 power-down modes stop mode stop mode is invoked by stop control register (stopcon) setting and the instruction stop. in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 3 ua at 5.5 v. all system functions stop when the clock "freezes," stop mode can be released of two ways : by an intr (interrupt with reset) or by a por (power on reset). using por to release stop mode stop mode is released when the reset signal goes active by power on reset (por): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are unknown states. when the oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h. using an intr to release stop mode stop mode is released when intr (interrupt with reset) occurs. intr occurs when falling/rising edge is detected at p0 during stop mode and it make system reset. note 1. do not use stop mode if you are using an external clock source because x in input must be cleared internally to v ss to reduce current leakage. 2. stop mode always be released by the system reset (intr or por) so the system register value and control register value are initialized as reset value. and when the reset occurs from intr, the prime register value will be retained but it will be unknown states if it occurs from por. so an application which is using stop mode should be added specific s/w which divide the system reset into stop mode releasing or power on reset. following programming tip can be useful for more understanding.
s3p80c5/c80c5/c80c8 reset reset and power-down 8- 7 f f programming tip ? to divide stop mode releasing and por. this example shows how to enter the stop mode and how to know it is stop mode releasing or power on reset . org 0100h ; reset address start di ; ld btcon,#03h ; enable basic timer counter. ld spl,#0ffh ; initialize the system register clr sym clr pp clr emt clr ipr ? ? ld p0conh,#00h ; initialize the control register ld p0conl,#00h ld p0pur,#0ffh ? ? ? check_ram: ; check the ram data whether it is stop mode releasing ; or power on reset ld r0,#0bfh ; if power on reset , go to por_reset chk_r cp r0,@r0 ; jr ne,por_reset dec r0 cp r0,#0b0h jr uge, chk_r stop_reset: ; stop mode releasing. jr main ; por_reset ld r0,#0ffh ;power on reset ;check ram data are failed so clear all ram data. ram_clr clr @r0 djnj r0,ramclr ld r0,#0bfh ;initialize the check ram data as default value .
reset reset and power-down s3p80c5/c80c5/c80c 8 8- 8 f f programming tip ? to divide stop mode releasing and por. (continued) chk_w ld @r0,r0 dec r0 cp r0,#0b0h jr uge,chk_w main: cp p0,#0ffh ; jr eq,ent_stop ? ? ? jp t,main ent_stop ld stopcon,#0a5h ;enter the stop mode. stop nop nop jp reset ? ? ?
s3p80c5/c80c5/c80c8 reset reset and power-down 8- 9 idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu and from all but the following peripherals, which remain active: ? interrupt logic ? timer 0 ? timer 1 ? counter a i/o port pins retain the mode (input or output) they had at the time idle mode was entered. idle mode release you can release idle mode in one of two ways: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slowest clock because of the hardware reset value for the clkcon register. if all external interrupts are masked in the imr register, a reset is the only way you can release idle mode. 2. activate any enabled interrupt ; internal or external. when you use an interrupt to release idle mode, the 2 -bit clkcon.4/clkcon.3 value remains unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt condition (iret) occurs, the instruction immediately following the one which initiated idle mode is executed. note only external interrupts with an rc delay built in to the pin circuit can be used to release stop mode without reset. to release idle mode, you can use either an external interrupt or an internally-generated interrupt.
reset reset and power-down s3p80c5/c80c5/c80c 8 8- 10 summary table of stop mode, and idle mode table 8-2. summary of each mode item/mode idle stop approach condition v dd is higher than v lvd (v lvd < v dd ). idle (instruction). v dd is higher than v lvd (v lvd < v dd ). stopcon a5h stop instruction release source interrupt t0/t1 interrupt counter a interrupt ext. interrupt (port0) reset por lvd wdt reset intr por
s3p80c5/c80c5/c80c8 i/o ports 9- 1 9 i/o ports overview the s3p80c5/c80c5/c80c8 microcontroller has three bit-programmable i/o ports, p0?p2. two ports, p0-p1, are 8-bit ports and p2 is a 3-bit port. this gives a total of 19 i/o pins in the s3p80c5/c80c5/c80c8"s 24-pin package. each port is bit-programmable and can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. for ir universal remote controller applications, ports 0, and1 are usually configured to the keyboard matrix and port 2 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a led. table 9-1 gives you a general overview of s3p80c5/c80c5/c80c8 i/o port functions. table 9-1. s3p80c5/c80c5/c80c8 port configuration overview port configuration options 0 8-bit general-purpose i/o port; input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all p0 pin circuits have noise filters and interrupt enable/disable (p0int) and pending control (p0pnd); pull-up resistors can be assigned to individual p0 pins using p0pur register settings. specially interrupt with reset(intr) is assigned to release stop mode with system reset. 1 8-bit general-purpose i/o port; input, open-drain output, or push-pull output. pull-up resistors can be assigned to individual p1 pins using p1pur register settings. 2 3-bit i/o port; input mode with or without pull-up, push-pull or open-drain output mode. rem and t0pwm can be assigned. port 2 pins have high current drive capability to support led applications. the port 2 data register contains three status bits: three for p2.0, p2.1 and p2.2 and one for remote controller carrier signal on/off status.
i/o ports s3p80c5/c80c5/c80c 8 9- 2 port data registers table 9-2 gives you an overview of the register locations of all three S3C80C5/c80c8 port data registers. data registers for ports 0, and 1 have the general format. note the data register for port 2, p2, contains three bits for p2.0, p2.1 and p2.2, and an additional status bit for carrier signal on/off. table 9-2. port data register summary register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w because port 2 is a 3-bit i/o port, the port 2 data register only contains values for p2.0, p2.1 and p2.2. the p2 register also contains values for p2.0, p2.1 and p2.2. the p2 register also contains a special carrier on/off bit(p2.5). see the port 2 description for details. all other s3p80c5/c80c5/c80c8 i/o ports are 8-bit. pull-up resistor enable registers note: pull-up resistors can be assigned to the port 2 pins, p2.0, p2.1 and p2.2 by marking the appropriate the port 2 control register,p2con. port0 pull-up resistor enable register (p0pur) e7h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 pull-up resistor enable bit: 0 = enable pull-up resistor 1 = disable pull-up resistor figure 9-1. s3p80c5/c80c5/c80c8 i/o port 0 data register format
s3p80c5/c80c5/c80c8 i/o ports 9- 3 port1 pull-up resistor enable register (p1pur) ech, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 pull-up resistor enable bit: 0 = disable pull-up resistor 1 = enable pull-up resistor note: pull-up resistors can be assigned to the port 2 pins, p2.0, p2.1 and p2.2 by marking the appropriate the port 2 control register, p2con. figure 9-2. s3p80c5/c80c5/c80c8 i/o port 1 data register format
i/o ports s3p80c5/c80c5/c80c 8 9- 4 port 0 port 0 is a general-purpose, 8-bit i/o port. it is bit-programmable. port 0 pins are accessed directly by read/write operations to the port 0 data register, p0 (set 1, e0h). the p0 pin circuits support pull-up resistor assignment using p0pur register settings and all pins have noise filters for external interrupt inputs. two 8-bit control registers are used to configure port 0 pins: p0conh (set 1, e8h) for the upper nibble pins, p0.7?p0.4, and p0conl (set 1, e9h) for lower nibble pins, p0.3?p0.0. each control register byte contains four bit-pairs and each bit-pair configures one pin (see figures 9-2 and 9-3). a hardware reset clears all p0 control and data registers to '00h'. a separate register, the port 0 interrupt control register, p0int (set 1, f1h), is used to enable and disable external interrupt input. you can poll the port 0 interrupt pending register, p0pnd to detect and clear pending conditions for these interrupts. the lower-nibble pins, p0.3?p0.0, are used for int3?int0 input (irq6), respectively. the upper nibble pins, p0.7?p0.4, are all used for int4 input (irq7). interrupts that are detected at any of these four pins are processed using the same vector address (e8h). port 0 , p0.0?p0.7, is assigned interrupt with reset(intr) to release stop mode with system reset. port 0 control register, high byte (p0conh) e8h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.7/int4 p0.4/int4 p0.6/int4 p0.5/int4 p0conh pin configureation settings: 00 01 10 11 input mode; interrupt on falling edges input mode; interrupt on rising and falling edges push-pull output mode input mode; interrupt on rising edges figure 9-3. port 0 high-byte control register (p0conh)
s3p80c5/c80c5/c80c8 i/o ports 9- 5 port 0 control register, low byte (p0conl) e9h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3/int3 p0.0/int0 p0.2/int2 p0.1/int1 p0conl pin configureation settings: 00 01 10 11 input mode; interrupt on falling edges input mode; interrupt on rising and falling edges push-pull output mode input mode; interrupt on rising edges figure 9-4. port 0 low-byte control register (p0conl) port 0 interrupt enable register (p0int) the port 0 interrupt control register, p0int, is used to enable and disable external interrupt input at individual p0 pins (see figure 10-5). to enable a specific external interrupt, you set its p0int.n bit to "1". you must also be sure to make the correct settings in the corresponding port 0 control register (p0conh, p0conl). port 0 interrupt pending register (p0pnd) the port 0 interrupt pending register, p0pnd, contains pending bits (flags) for each port 0 interrupt (see figure 10 -6). when a p0 external interrupt is acknowledg ed by the cpu, the service routine must clear the pending condition by writing a "0" to the appropriate pending flag in the p0pnd register (writing a "1" to the pending bit has no effect). note a hardware reset(intr, por) clears the p0int and p0pnd registers to '00h'. for this reason, the application program's initialization routine must enable the required external interrupts for port 0, and for the other i/o ports.
i/o ports s3p80c5/c80c5/c80c 8 9- 6 port 0 interrup enable register (p0int) f1h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 interrupt enable bits: 0 1 disable interrupt enable interrupt p0.7/int4 p0.6/int4 p0.5/int4 p0.4/int4 p0.3/int3 p0.2/int2 p0.1/int1 p0.0/int0 figure 9-5. port 0 external interrupt control register (p0int) port 0 interrup pending register (p0pnd) f2h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 interrupt pending bits: 0 0 1 1 interrupt not pending clear p0.n pending condition (when write) p0.n interrupt is pending no effect (when write) p0.7/int4 p0.6/int4 p0.5/int4 p0.4/int4 p0.3/int3 p0.2/int2 p0.1/int1 p0.0/int0 figure 9-6. port 0 external interrupt pending register (p0pnd)
s3p80c5/c80c5/c80c8 i/o ports 9- 7 port 1 port 1 is a bit-programmable 8-bit i/o port. port 1 pins are accessed directly by read/write operations to the port 1 data register, p1 (set 1, e1h). to configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers: p1conh (set 1, eah) for the upper nibble pins, p1.7?p1.4, and p1conl (set 1, ebh) for the lower nibble pins, p1.3?p1.0. each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see figures 9-6 and 9-7). following a hardware reset, the port 1 control registers are cleared to '00h', configuring port 0 initially to input mode. to assign pull-up resistors to p1 pins, you make the appropriate settings to the port 1 pull-up resistor enable register, p1pur. port 1 control register, high byte (p1conh) eah, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.7 p1.4 p1.6 p1.5 p1conh pin configureation settings: 00 01 10 11 input mode open-drain output mode push-pull output mode invalid setting figure 9-7. port 1 high-byte control register (p1conh)
i/o ports s3p80c5/c80c5/c80c 8 9- 8 port 1 control register, low byte (p1conl) ebh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.3 p1.0 p1.2 p1.1 p1conl pin configureation settings: 00 01 10 11 input mode open-drain output mode push-pull output mode invalid setting figure 9-8. port 1 low-byte control register (p1conl)
s3p80c5/c80c5/c80c8 i/o ports 9- 9 port 2 port 2 is a bit-programmable 3-bit i/o port. port 2 pins are accessed directly by read/write operations to the port 2 data register, p2 (set 1, e2h). you can configure port 2 pins individually to input mode, open-drain output mode, or push-pull output mode. p2.0, p2.1 and p2.2 are configured by writing 6-bit data value to the port 2 control register, p2con. you can configure these pins to support input functions (input mode, with or without pull-up, for t0ck) or output functions (push-pull or open-drain output mode for rem and timer 0 pwm). port 2 pins have high current drive capability to support led applications. a reset operation clears p2con to '00h', selecting input mode as the initial port 2 function. port 2 control register (p2con) f0h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.2 p2.2 p2.1 p1.0 p2.1 alternative function enable 0 1 normal i/o function rem/t0ck p2.0 alternative function enable 0 1 normal i/o function t0pwm p2con pin configuration setting: 00 01 10 11 c-mos input mode open-drain output mode push-pull output mode c-mos input mode with pull-up figure 9-9. port 2 control register (p2con)
i/o ports s3p80c5/c80c5/c80c 8 9- 10 port 2 data register (p2) e2h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for S3C80C5 p2.0/t0_pwm carrier on/off for remote controller p2.2 p2.1/rem/tock not used for S3C80C5 figure 9-10. port 2 data register (p2)
s3p80c5/c80c5/c80c8 basic timer and timer 0 10- 1 10 basic timer and timer 0 module overview the s3p80c5/c80c5/c80c8 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. the 8 -bit timer/counter is called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a system reset clears btcon. this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code '1010b' to the basic timer register control bits btcon.7?btcon.4. for more reliability, we recommend to use the watch-dog timer function in remote controller and hand-held product application.
basic timer and timer 0 s3p80c5/c 80c5/c80c8 10- 2 basic timer control register (btcon) d3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb watchdog function enable bits: 1010b = disable watchdog timer other value = enable watchdog timer divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers basic timer input clock selection bits: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 01 10 11 f osc /4096 f osc /1024 f osc /128 invalid selection figure 10-1. basic timer control register (btcon)
s3p80c5/c80c5/c80c8 basic timer and timer 0 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by enabling the watchdog function. a reset clears btcon to '00h', automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting),divided by 4096, as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. timer 0 control register (t0con) you use the timer 0 control register, t0con, to ? select the timer 0 operating mode (interval timer) ? select the timer 0 input clock frequency ? clear the timer 0 counter, t0cnt ? enable the timer 0 overflow interrupt or timer 0 match interrupt ? clear timer 0 match interrupt pending conditions t0con is located in set 1, at address d2h, and is read/write addressable using register addressing mode. a reset clears t0con to '00h'. this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables all timer 0 interrupts. you can clear the timer 0 counter at any time during normal operation by writing a "1" to t0con.3. the timer 0 overflow interrupt (t0ovf) is interrupt level irq0 and has the vector address fah. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer 0 match interrupt (irq0, vector fch), you must write t0con.1 to "1". to detect a match interrupt pending condition, the application program polls t0con.0. when a "1" is detected, a timer 0 match interrupt is pending. when the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0.
basic timer and timer 0 s3p80c5/c 80c5/c80c8 10- 4 timer 0 control register (t0con) d2h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 00 = f osc /4096 01 = f osc /256 10 = f osc /8 11 = external clock (p2.1/t0ck) timer 0 operating mode selection bits: 00 = interval mode 01 = overflow mode (ovf interrupt can occur) 10 = overflow mode (ovf interrupt can occur) 11 = pwm mode (ovf interrupt can occur) timer 0 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer 0 match interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 0 match interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (write) 1 = interrupt is pending figure 10-2. timer 0 control register (t0con)
s3p80c5/c80c5/c80c8 basic timer and timer 0 10- 5 timer 0 function description timer 0 interrupts (irq0, vectors fah and fch) the timer 0 module can generate two interrupts: the timer 0 overflow interrupt (t0ovf), and the timer 0 match interrupt (t0int). t0ovf is interrupt level irq0, vector fah. t0int also belongs to interrupt level irq0, but is assigned the separate vector address, fch. a timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. the t0int pending condition must, however, be cleared by the application?s interrupt service routine by writing a "0" to the t0con.0 interrupt pending bit. interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0 reference data register, t0data. the match signal generates a timer 0 match interrupt (t0int, vector fch) and clears the counter. if, for example, you write the value ?10h? to t0data and ?0bh? to t0con, the counter will increment until it reaches ?10h?. at this point, the t0 interrupt request is generated, the counter value is reset, and counting resumes. with each match, the level of the signal at the timer 0 output pin is inverted (see figure 10-3). interrupt enable/disable (t0con.1) pending (t0con.0) ctl p2.0 t0con.5 t0con.4 match signal t0con.3 irq0(int) r (clear) clk match data register buffer register comparator counter figure 10-3. simplified timer 0 function diagram: interval timer mode
basic timer and timer 0 s3p80c5/c 80c5/c80c8 10- 6 pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0pwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ?ffh?, and then continues incrementing from ?00h?. although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the t0pwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk 256 (see figure 11-4). interrupt enable/disable (t0con.1) ctl p2.0/ t0pwm t0con.5 t0con.4 match signal t0con.3 irq0(t0int) irq0 (t0ovf) clk match data register buffer register comparator counter t0ovf (t0con.0) high level when data > counter; low level when data < counter _ note: interrupts are usually not used when timer 0 is configurared to operate in pwm mode pnd figure 10-4. simplified timer 0 function diagram: pwm mode
s3p80c5/c80c5/c80c8 basic timer and timer 0 10- 7 during a power-on reset operation, the cpu is idle during the required oscillation stabilizatiin interval (until bit 4 of the basic timer counter overflows). it is available only in using interval mode. notes: 1. 2. bits 7,6 bit 0 x in bits 3,2 reset or stop clear data bus bit 1 data bus match signal t0con.3 t0ovf 8-bit basic counter (read-only) ovf bit 2 bit 3 ovf div r 1/4096 1/1024 1/128 p2.1/t0ck bit 1 pnd t0con.0 match (2) p2.0 bits 5,4 t0pwm t0int reset data bus basic timer control register timer 0 control register mux mux div 1/4096 1/1024 1/128 r basic timer control register (write '1010xxxxb' to disable) 8-bit up-counter (read-only) r 8-bit comparator timer 0 buffer reg timer 0 data register (read/write) clear figure 10-5. basic timer and timer 0 block diagram
basic timer and timer 0 s3p80c5/c 80c5/c80c8 10- 8 f f programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specifications: org 0100h reset di ; disable all interrupts ld btcon,#03h ; enable the watchdog timer ld clkcon,#18h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts ? ? ? main ld btcon,#02h ; enable the watchdog timer ; basic timer clock: f osc /4096 ; clear basic timer counter nop nop ? ? ? jp t,main ? ? ?
s3p80c5/c80c5/c80c8 basic timer and timer 0 10- 9 f f programming tip ? programming timer 0 this sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. the program parameters are as follows: ? timer 0 is used in interval mode; the timer interval is set to 4 milliseconds ? oscillation frequency is 4 mhz ? general register 60h (page 0) ? 60h + 61h + 62h + 63h + 64h (page 0) is executed after a timer 0 interrupt org 0fah ; timer 0 overflow inter rupt vector t0over org 0fch ; timer 0 match/capture interrupt vector t0int org 0100h reset di ; disable all interrupts ld btcon,#0aah ; disable the watchdog timer ld clkcon,#18h ; select non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? ld t0con,#4bh ; write '01001011b' ; input clock is f osc /256 ; interval timer mode ; enable the timer 0 interrupt ; disable the timer 0 overflow interrupt ld t0data,#5dh ; set timer interval to 4 milliseconds ; (4 mhz/256) ? (93 + 1) = 0.166 khz (6 ms) srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts ? ? ?
basic timer and timer 0 s3p80c5/c 80c5/c80c8 10- 10 f f programming tip ? programming timer 0 (continued) t0int push rp0 ; save rp0 to stack srp0 #60h ; rp0 ? 60h inc r0 ; r0 ? r0 + 1 add r2,r0 ; r2 ? r2 + r0 adc r3,r2 ; r3 ? r3 + r2 + carry adc r4,r0 ; r4 ? r4 + r0 + carry cp r0,#32h ; 50 6 = 300 ms jr ult,no_300ms_set bits r1.2 ; bit setting (61.2h) no_300ms_set: ld t0con,#42h ; clear pending bit pop rp0 ; restore register pointer 0 value t0over iret ; return from interrupt service routine
s3p80c5/c80c5/c80c8 timer 1 11- 1 11 timer 1 overview the S3C80C5/c80c8 microcontroller has a 16-bit timer/counter called timer 1 (t1). for universal remote controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal. timer 1 has the following components: ? one control register, t1con (set 1, fah, r/w) ? two 8-bit counter registers, t1cnth and t1cntl (set 1, f6h and f7h, read-only) ? two 8-bit reference data registers, t1datah and t1datal (set 1, f8h and f9h, r/w) ? a 16-bit comparator you can select one of the following clock sources as the timer 1 clock: ? oscillator frequency (f osc ) divided by 4, 8, or 16 ? internal clock input from the counter a module (counter a flip/flop output) you can use timer 1 in two ways: ? as a normal free run counter, generating a timer 1 overflow interrupt (irq1, vector f4h) at programmed time intervals. ? to generate a timer 1 match interrupt (irq1, vector f6h) when the 16-bit timer 1 count value matches the 16-bit value written to the reference data registers. in the S3C80C5/c80c8 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1 match.
timer 1 s3p80c5/c80c5/c80c8 11- 2 timer 1 overflow interrupt timer 1 can be programmed to generate an overflow interrupt (irq1, f4h) whenever an overflow occurs in the 16-bit up counter. when you set the timer 1 overflow interrupt enable bit, t1con.2, to ?1?, the overflow interrupt is generated each time the 16-bit up counter reaches ?ffffh?. after the interrupt request is generated, the counter value is automatically cleared to ?00h? and up counting resumes. by writing a ?1? to t1con.3, you can clear/reset the 16-bit counter value at any time during program operation. timer 1 match interrupt timer 1 can also be used to generate a match interrupt (irq1, vector f6h) whenever the 16-bit counter value matches the value that is written to the timer 1 reference data registers, t1datah and t1datal. when a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ?00h?. in match mode, program software can poll the timer 1 match interrupt pending bit, t1con.0, to detect when a timer 1 match interrupt pending condition exists (t1con.0 = "1"). when the interrupt request is acknowledged by the cpu and the service routine starts, the interrupt service routine for vector f6h must clear the interrupt pending condition by writing a ?0? to t1con.0. interrupt enable/disable (t1con.2) pending (t1con.0) ctl t1con.5 t1con.4 match signal t1con.3 irq1(t1int) r (clear) clk match timer 1 data high/low buffer register timer 1 high/low buffer register 16-bit comparator 16-bit up counter (read-only) figure 11-1. simplified timer 1 function diagram: interval timer mode
s3p80c5/c80c5/c80c8 timer 1 11- 3 notes: match signal is occured only in interval mode. t1con.7-.6 t1con.3 match signal t1ovf ovf m u x match (note) irq1 data bus mux 16-bit up-counter (read-only) r 16-bit comparator timer 1 high/low buffer register timer 1 data high/low register caof (t-f/f) f osc /4 f osc /8 f osc /16 clear t1con.3 t1con.2 irq1 t1con.5-.4 t1con.1 t1con.0 figure 11-2. timer 1 block diagram
timer 1 s3p80c5/c80c5/c80c8 11- 4 timer 1 control register (t1con) the timer 1 control register, t1con, is located in set 1, fah, and is read/write addressable. t1con contains control settings for the following t1 functions: ? timer 1 input clock selection ? timer 1 operating mode selection ? timer 1 16-bit down counter clear ? timer 1 overflow interrupt enable/disable ? timer 1 match interrupt enable/disable ? timer 1 interrupt pending control (read for status, write to clear) a reset operation clears t1con to ?00h?, selecting f osc divided by 4 as the t1 clock, configuring timer 1 as a normal interval timer, and disabling the timer 1 interrupts. timer 1 control register (t1con) fah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 1 counter clear bit: 0 = no effect 1 = clear the timer 1 counter (when write) timer 1 input clock selection bits: 00 = f osc /4 01 = f osc /8 10 = f osc /16 11 = internal clock (t-f/f) timer 1 operating mode selection bits: 00 = interval mode 01 = overflow mode (ovf interrupt can occur) 01 = overflow mode (ovf interrupt can occur) 01 = overflow mode (ovf interrupt can occur) timer 1 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer 1 match interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 1 match interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (write) 1 = interrupt is pending figure 11-3. timer 1 control register (t1con)
s3p80c5/c80c5/c80c8 timer 1 11- 5 timer 1 counter low-byte register (t1cntl) f7h, set 1, r .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : 00h timer 1 counter high-byte register (t1cnth) f6h, set 1, r .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : 00h timer 1 data high-byte register (t1datah) f8h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : ffh timer 1 data low-byte register (t1datal) f9h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : ffh figure 11-4. timer 1 registers
timer 1 s3p80c5/c80c5/c80c8 11- 6 notes
s3p80c5/c80c5/c80c8 counter a 12- 1 12 counter a overview the s3p80c5/c80c5/c80c8 microcontroller has an 8-bit counter called counter a. counter a, which can be used to generate the carrier frequency, has the following components (see figure 12-1): ? counter a control register, cacon ? 8-bit down counter with auto-reload function ? two 8-bit reference data registers, cadatah and cadatal counter a has two functions: ? as a normal interval timer, generating a counter a interrupt (irq4, vector ech) at programmed time intervals. ? to supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow interrupt.
counter a s3p 80c5/c80c5/c80c8 12- 2 notes: the value of the cadatal register is loaded into the 8-bit counter when the operaion of the counter a starts. if a borrow occurs in the counter, the value of the cadatah register is loaded into the 8-bit counter. however, if the next borrow ovvurs, the value of the cadatal register is loaded into the 8-bit counter. cacon.6-.7 mux div 1 div 2 div 4 div 8 clk cacon.0 (caof) to other block (p3.1/rem) repeat control interrupt control cacon.4-.5 cacon.2 f osc counter a data high byte register int.gen. mux 8-bit down counter counter a data low byte register cacon.3 irq4 (caint) data bus figure 12-1. counter a block diagram
s3p80c5/c80c5/c80c8 counter a 12- 3 counter a control register (cacon) the counter a control register, cacon, is located in set 1, bank 0, f3h, and is read/write addressable. cacon contains control settings for the following functions (see figure 12-2): ? counter a clock source selection ? counter a interrupt enable/disable ? counter a interrupt pending control (read for status, write to clear) ? counter a interrupt time selection counter a control register (cacon) f3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb counter a input clock selection bits: 00 = f osc 01 = f osc /2 10 = f osc /4 11 = f osc /8 counter a output flip-flop control bit: 0 = t-ff is low 1 = t-ff is high counter a mode selection bit: 0 = one-shot mode 1 = repeating mode counter a interrupt selection bits: 00 = elapsed time for low data value 01 = elapsed time for high data value 10 = elapsed time for low and high data values 11 = invalid setting counter a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt counter a start/stop bit: 0 = stop counter a 1 = start counter a figure 12-2. counter a control register (cacon)
counter a s3p 80c5/c80c5/c80c8 12- 4 counter a data low-byte register (cadatal) f5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : ffh counter a data high-byte register (cadatah) f4h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb reset value : ffh figure 12-3. counter a registers counter a pulse width calculations t low t high t low to generate the above repeated waveform consisted of low period time, t low , and high period time, t high . when caof = 0, t low = (cadatal + 2) x 1/fxx, 0h < cadatal < 100h, where fx = the selected clock. t h igh = (cadatah + 2) x 1/fxx, 0h < cadatah < 100h, where fx = the selected clock. when caof = 1, t low = (cadatah + 2) x 1/fxx, 0h < cadatah < 100h, where fx = the selected clock. t high = (cadatal + 2) x 1/fxx, 0h < cadatal < 100h, where fx = the selected clock. to make t low = 24 us and t high = 15 us. f osc = 4 mhz, fx = 4 mhz/4 = 1 mhz [method 1] when caof = 0, t low = 24 us = (cadatal + 2) / fx = (cadatal + 2) 1us, cadatal = 22. t high = 15 us = (cadatah + 2) / fx = (cadatah + 2) 1us, cadatah = 13. [method 2] when caof = 1, t high = 15 us = (cadatal + 2) / fx = (cadatal + 2) 1us, cadatal = 13. t low = 24 us = (cadatah + 2) / fx = (cadatah + 2) 1us, cadatah = 22.
s3p80c5/c80c5/c80c8 counter a 12- 5 low high high low 0h counter a clock caof = '0' cadatal = 01-ffh cadatah = 001h caof = '0' cadatal = 00h cadatah = 01-ffh caof = '0' cadatal = 00h cadatah = 00h caof = '1' cadatal = 00h cadatah = 00h e0h 0h counter a clock caof = '0' cadatal = deh cadatah = 1eh caof = '0' cadatal = deh cadatah = 1eh caof = '1' cadatal = 7eh cadatah = 7eh caof = '0' cadatal = 7eh cadatah = 7eh e0h 20h 20h 80h 80h 80h 80h figure 12-4. counter a output flip-flop waveforms in repeat mode
counter a s3p 80c5/c80c5/c80c8 12- 6 f f programming tip ? to generate 38 khz, 1/3duty signal through p2.1 this example sets counter a to the repeat mode, sets the oscillation frequency as the counter a clock source, and cadatah and cadatal to make a 38 khz,1/3 duty carrier frequency. the program parameters are: 17.59 m s 8.795 m s 37.9 khz 1/3 duty ? counter a is used in repeat mode ? oscillation frequency is 4 mhz (0.25 m s) ? cadatah = 8.795 m s / 0.25 m s = 35.18, cadatal = 17.59 m s / 0.25 m s = 70.36 ? set p2.1 c-mos push-pull output and caof mode. org 0100h ; reset address start di ? ? ? ld cadatal,#(70-2) ; set 17.5 m s ld cadatah,#(35-2) ; set 8.75 m s ; ld p2con,#10101010b ; set p2 to c-mos push-pul l output. ; set p2.1 to rem output ; ld cacon,#00000110b ; clock source ? f osc ; disable counter a interrupt. ; select repeat mode for counter a. ; start counter a operation. ; set counter a output flip-flop(caof) high. ; ld p2,#20h ; set p2.5(carrier on/off) to high. ; this command generates 38 khz, 1/3duty pulse signal ; through p2.1 ; ? ? ?
s3p80c5/c80c5/c80c8 counter a 12- 7 f f programming tip ? to generate a one pulse signal through p2.1 this example sets counter a to the one shot mode, sets the oscillation frequency as the counter a clock source, and cadatah and cadatal to make a 40 m s width pulse. the program parameters are: 40 m s ? counter a is used in one shot mode ? oscillation frequency is 4 mhz (1 clock = 0.25 m s) ? cadatah = 40 m s / 0.25 m s = 160, cadatal = 1 ? set p2.1 c-mos push-pull output and caof mode. org 0100h ; reset address start di ? ? ld cadatah,# (160-2) ; set 40 m s ld cadatal,# 1 ; set any value except 00h ; ld p2con,#10101010b ; set p2 to c-mos push-pull output. ; set p2.1 to rem output ; ld cacon,#00000001b ; clock source ? f osc ; disable counter a interrupt. ; select one shot mode for counter a. ; stop counter a operation. ; set counter a output flip-flop (caof) high ld p2,#20h ; set p2.5(carrier on/off) to high. ? ? ? pulse_out: ld cacon,#00000101b ; start counter a operation ; to make the pulse at t his point. ? ; after the instruction is executed, 0.75 m s is required ? ; before the falling edge of the pulse starts. ?
counter a s3p 80c5/c80c5/c80c8 12- 8 notes
s3p80c5/c80c5/c80c8 electrical data 13- 1 13 electrical data overview in this section, s3p80c5/c80c5/c80c8 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retentio n supply voltage in stop mode ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? input timing for external interrupts (port 0) ? oscillation characteristics ? oscillation stabilization time
electrical data s3 p80c5/c80c5/c80c8 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in ? ? 0.3 to v dd + 0.3 v output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0, 1, and 2 + 100 total pin current for port 3 + 40 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 13-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 3.6 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 4mhz (instruction clock = 0.67 mhz) 1.7 ? 3.6 v input high voltage v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v v ih2 x in v dd ? 0.3 v dd input low voltage v il1 all input pins except v il2 and v il3 0 ? 0.2 v dd v v il2 x in 0.3 output high voltage v oh1 v dd = 2.4 v, i oh = ? 6 ma port 2.1 only, t a = 25 c v dd ? 0.7 v v oh2 v dd = 2.4 v, i oh = ? 2.2ma port 2.0, 2.2, t a = 25 c v dd - 0.7 ? ? v oh3 v dd = 2.4 v, i oh = ? 1 ma all output pins except port2, t a = 25 c v dd - 1.0 ? ?
s3p80c5/c80c5/c80c8 electrical data 13- 3 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 3.6 v) parameter symbol conditions min typ max unit output low voltage v ol1 v dd = 2.4 v, i ol = 12 ma, port 2.1 only, t a = 25 c 0.4 0.5 v ol2 v dd = 2.4 v, i ol = 5 ma port 2.0,2.2, t a = 25 c ? 0.4 0.5 v ol3 i ol = 1 ma ports 0 and 1, t a = 25 c 0.4 1.0 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 1 a i lih2 v in = v dd , x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out ? ? ? 1 a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 a output low leakage current i lol v out = 0 v all output pins ? ? ? 1 a pull-up resistors r l1 v dd = 2.4v, v in = 0 v; t a = 25 c , ports 0-2 44 55 95 k w supply current (note) i dd1 v dd = 3.6 v 10% 4-mhz crystal ? 2.6 5 ma i dd2 idle mode; v dd = 3.6 v 10 % 4-mhz crystal ? 0.7 2.0 i dd3 stop mode; v dd = 3.6 v ? 1 6 ua note : supply current does not include current drawn through internal pull-up resistors or external output current loads.
electrical data s3 p80c5/c80c5/c80c8 13- 4 table 13-3. characteristics of low voltage detect circuit (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit hysteresys voltage of lvd (slew rate of lvd) d v ? ? 30 300 mv low level detect voltage (S3C80C5/c80c8) v lvd ? 1.70 1.90 2.1 v table 13-4. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.0 ? 3.6 v data retention supply current i dddr v dddr = 1.0 v stop mode ? ? 1 a table 13-5. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 13-6. a.c. electrical characteristics (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit interrupt input, high, low width t inth , t intl p0.0?p0.7, v dd = 3.6 v 200 300 ? ns
s3p80c5/c80c5/c80c8 electrical data 13- 5 t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. figure 13-1. input timing for external interrupts (port 0) table 13-7. oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit crystal x out x in c2 c1 cpu clock oscillation frequency 1 ? 4 mhz ceramic xt out xt in c2 c1 cpu clock oscillation frequency 1 ? 4 mhz external clock x out x in external clock open pin x in input frequency 1 ? 4 mhz
electrical data s3 p80c5/c80c5/c80c8 13- 6 table 13-8. oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 3.6 v) oscillator test condition min typ max unit main crystal f osc > 400 khz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization wait time t wait when released by a reset (1) ? 2 16 / f osc ? ms t wait when released by an interrupt (2) ? ? ? ms notes : 1. f osc is the oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. 1.33 mhz 250 khz 8.32 khz 1 2 3 4 5 6 7 supply voltage (v) instruction clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) a 1.7 v: 4 mhz b 2.0 v: 8 mhz 1.00 mhz a b 500 khz 670 khz instruction clock 8 mhz 6 mhz 4 khz instruction clock 400 khz figure 13-2. operating voltage range of s3p80c5/c80c5/c80c8
s3p80c5/c80c5/c80c8 mechanical data 14- 1 14 mechanical data overview the s3p80c5/c80c5/c80c8 microcontroller is currently available in a 24-pin sop and sdip package. note : dimensions are in millimeters. 24-sop-375 10.30 0 .30 #13 #24 #1 #12 15.74 max 15.34 0 .20 (0.69) 0-8 0.15 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.38 0.10 max + 0.10 - 0.05 1.27 figure 14-1. 24-pin sop package mechanical data
mechanical data s3p80c5/c8 0c5/c80c8 14- 2 note : dimensions are in millimeters. 23.35 max 22.95 0 .20 (1.70) 24-sdip-300 6.40 0 .20 #24 #1 0.46 0.10 0.89 0.10 #13 #12 0-15 0.25 + 0.10 - 0.05 7.62 3.25 0.20 5.08 max 1.778 0.51 min 3.30 0.30 figure 14-2. 24-pin sdip package mechanical data
(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) note : please one more check whether the selected device is s3c80a4/c80a8/c80a5 or s 3c80b4/c80b8/c80b5. s3c8 series mask rom order form product description: device number: S3C80C5 s3c80c8 s3c__________- ___________(write down the rom code number) (note) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: f f for what kind of product will you be using this orde r? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) note : please one more check whether the selected device is s3c80a4/c80a8/c80a5 or s 3c80b4/c80b8/c80b5. s3c8 series request for production at customer risk customer information: company name: ________________________________________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: S3C80C5 s3c80c8 s3c__________- ___________(write down the rom code number) (note) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: ________________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ ______ (person placing the risk order) (sec sales representative)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) note: please one more check whether the selected device is s3p80a4/p80a8/p80a5 or s3p80b4/p80b8/p80b5. S3C80C5/c80c8 mask option selection form device number: S3C80C5 s3c80c8 s3c8__________- ___________(write down the rom code number) (note) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ please answer the following questions: f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) note: please one more check whether the selected device is s3p80a4/p80a8/p80a5 or s3p80b4/p80b8/p80b5. s3c8 series otp factory writing order form (1/2) product description: device number: s3p80c5 s3p8__________- ___________(write down the rom code number) (note) product order form: package pellet wafer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: f f what is the purpose of this order? new product development upgrade of an existing product replacement of an existing microcontroller other if you are replacing an existing microcontroller, please indicate the former microcontroller name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) note : please one more check whether the selected device is s3p80a4/p80a8/p80a5 or s3p80b4/p80b8/p80b5. S3C80C5/c80c8 otp factory writing order form (2/2) device number: s3p80c5 s3p8__________- ___________(write down the rom code number) (note) customer checksums: _______________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ read protection (1) : yes no please answer the following questions: f f are you going to co ntinue ordering this device? yes no if so, how much will you be ordering? _________________ pcs f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application __________________________________________________________________________ notes 1. once you choose a read protection, you cannot read again the programming code from the eprom. 2. otp writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer. samsung does not take on any responsibility for errors occurred from the writing program.
book spine text samsung logo s3p80c5/c80c5/c80c8 microcontroller s user's manual, rev. 1 may 2002

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